diff -x .svn -urN linux-2.6.8-rc2/arch/arm/boot/bootp/bootp.lds linux-2.6.8-rc2-pnp1/arch/arm/boot/bootp/bootp.lds --- linux-2.6.8-rc2/arch/arm/boot/bootp/bootp.lds 2004-07-27 14:08:03.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/boot/bootp/bootp.lds 1970-01-01 01:00:00.000000000 +0100 @@ -1,30 +0,0 @@ -/* - * linux/arch/arm/boot/bootp/bootp.lds - * - * Copyright (C) 2000-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0; - .text : { - _stext = .; - *(.start) - *(.text) - initrd_size = initrd_end - initrd_start; - _etext = .; - } - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } -} diff -x .svn -urN linux-2.6.8-rc2/arch/arm/boot/compressed/head-xscale.S linux-2.6.8-rc2-pnp1/arch/arm/boot/compressed/head-xscale.S --- linux-2.6.8-rc2/arch/arm/boot/compressed/head-xscale.S 2004-07-27 14:08:03.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/boot/compressed/head-xscale.S 2004-07-27 13:59:07.000000000 +0200 @@ -66,4 +66,9 @@ mov r7, #MACH_TYPE_IQ80310 #endif +#ifdef CONFIG_ARCH_PXA_PNP2110 + @ FIXME: fix bootloader, then remove... + mov r7, #(MACH_TYPE_PNP2110 & 0xFF00) + add r7, r7, #(MACH_TYPE_PNP2110 & 0xFF) +#endif diff -x .svn -urN linux-2.6.8-rc2/arch/arm/configs/csb226_defconfig linux-2.6.8-rc2-pnp1/arch/arm/configs/csb226_defconfig --- linux-2.6.8-rc2/arch/arm/configs/csb226_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/configs/csb226_defconfig 2004-07-27 13:59:09.000000000 +0200 @@ -0,0 +1,704 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +CONFIG_MMU=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_STANDALONE=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_IKCONFIG is not set +# CONFIG_EMBEDDED is not set +CONFIG_KALLSYMS=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# System Type +# +# CONFIG_ARCH_ADIFCC is not set +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP3XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set + +# +# CLPS711X/EP721X Implementations +# + +# +# Epxa10db +# + +# +# Footbridge Implementations +# + +# +# IOP3xx Implementation Options +# +# CONFIG_ARCH_IOP310 is not set +# CONFIG_ARCH_IOP321 is not set + +# +# IOP3xx Chipset Features +# + +# +# Intel PXA250/210 Implementations +# +CONFIG_ARCH_CSB226=y +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_ARCH_INNOKOM is not set +# CONFIG_ARCH_LOGODL is not set +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_ARCH_TRIZEPS2 is not set + +# +# SA11x0 Implementations +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_MINICACHE=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +CONFIG_XSCALE_PMU=y + +# +# General setup +# +# CONFIG_ZBOOT_ROM is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=y +CONFIG_PCMCIA_DEBUG=y +# CONFIG_TCIC is not set + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set +# CONFIG_PM is not set +# CONFIG_PREEMPT is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="root=/dev/nfs mem=32M ip=dhcp console=ttyS0,19200" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_EDB7312 is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play support +# +CONFIG_PNP=y +CONFIG_PNP_DEBUG=y + +# +# Protocols +# +# CONFIG_ISAPNP is not set +# CONFIG_PNPBIOS is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_NETFILTER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_NET_SB1000 is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_SMC91X is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +CONFIG_NET_RADIO=y + +# +# Obsolete Wireless cards support (pre-802.11) +# +# CONFIG_STRIP is not set +# CONFIG_PCMCIA_WAVELAN is not set +# CONFIG_PCMCIA_NETWAVE is not set + +# +# Wireless 802.11 Frequency Hopping cards support +# +# CONFIG_PCMCIA_RAYCS is not set + +# +# Wireless 802.11b ISA/PCI cards support +# +CONFIG_HERMES=y + +# +# Wireless 802.11b Pcmcia/Cardbus cards support +# +CONFIG_PCMCIA_HERMES=y +# CONFIG_AIRO_CS is not set +# CONFIG_PCMCIA_ATMEL is not set +# CONFIG_PCMCIA_WL3501 is not set +CONFIG_NET_WIRELESS=y +# CONFIG_HOSTAP is not set + +# +# Token Ring devices +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +# CONFIG_NET_PCMCIA is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_TSLIBDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set +# CONFIG_SERIO_I8042 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_DZ is not set +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set + +# +# L3 serial bus support +# +# CONFIG_L3 is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_RAW_DRIVER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS=y +# CONFIG_DEVPTS_FS_XATTR is not set +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# +# CONFIG_MCP is not set + +# +# Console Switches +# +# CONFIG_SWITCHES is not set + +# +# USB support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff -x .svn -urN linux-2.6.8-rc2/arch/arm/configs/innokom_defconfig linux-2.6.8-rc2-pnp1/arch/arm/configs/innokom_defconfig --- linux-2.6.8-rc2/arch/arm/configs/innokom_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/configs/innokom_defconfig 2004-07-27 13:59:09.000000000 +0200 @@ -0,0 +1,668 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +CONFIG_MMU=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_STANDALONE=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_HOTPLUG is not set +# CONFIG_IKCONFIG is not set +# CONFIG_EMBEDDED is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# System Type +# +# CONFIG_ARCH_ADIFCC is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP3XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_VERSATILE_PB is not set + +# +# Intel PXA2xx Implementations +# +# CONFIG_ARCH_CSB226 is not set +CONFIG_ARCH_INNOKOM=y +# CONFIG_ARCH_LOGODL is not set +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_ARCH_PXA_PNP2110 is not set +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_ARCH_TRIZEPS2 is not set +CONFIG_PXA25x=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_MINICACHE=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +CONFIG_XSCALE_PMU=y + +# +# General setup +# +# CONFIG_ZBOOT_ROM is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Generic Driver Options +# +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_PM is not set +# CONFIG_PREEMPT is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="root=/dev/nfs mem=32M ip=dhcp console=ttyS0,19200" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_INNOKOM=y +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_EDB7312 is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_ARM_SMC91X=y +# CONFIG_ARM_SMC91X_TX_DMA is not set +CONFIG_ARM_SMC91X_THROTTLE_TX=y +CONFIG_ARM_SMC91X_DISABLE_OVER=y +# CONFIG_CIRRUS is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set +# CONFIG_SERIO_I8042 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_ISA is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_SCx200_ACB is not set + +# +# Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set + +# +# Other I2C Chip support +# +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_RTC8564 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_SYSFS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +CONFIG_DEVFS_DEBUG=y +# CONFIG_DEVPTS_FS_XATTR is not set +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# Misc devices +# + +# +# USB support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_NET2280 is not set +CONFIG_USB_GADGET_PXA2XX=y +CONFIG_USB_PXA2XX=y +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_SA1100 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff -x .svn -urN linux-2.6.8-rc2/arch/arm/configs/pnp2110_defconfig linux-2.6.8-rc2-pnp1/arch/arm/configs/pnp2110_defconfig --- linux-2.6.8-rc2/arch/arm/configs/pnp2110_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/configs/pnp2110_defconfig 2004-07-27 13:59:09.000000000 +0200 @@ -0,0 +1,728 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +CONFIG_MMU=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +# CONFIG_CLEAN_COMPILE is not set +# CONFIG_STANDALONE is not set +CONFIG_BROKEN=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_HOTPLUG=y +# CONFIG_IKCONFIG is not set +# CONFIG_EMBEDDED is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_GPIO=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# System Type +# +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP3XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_VERSATILE_PB is not set + +# +# Intel PXA2xx Implementations +# +# CONFIG_ARCH_CSB226 is not set +# CONFIG_ARCH_INNOKOM is not set +# CONFIG_ARCH_LOGODL is not set +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_MAINSTONE is not set +CONFIG_ARCH_PXA_PNP2110=y +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_ARCH_TRIZEPS2 is not set +CONFIG_PXA25x=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_MINICACHE=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_XSCALE_PMU=y + +# +# General setup +# +CONFIG_FPBUS=y +CONFIG_FPBUS_NGE=y +CONFIG_FPBUS_NGE_TB2=m +# CONFIG_ZBOOT_ROM is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 + +# +# PCMCIA/CardBus support +# +# CONFIG_PCMCIA is not set + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Generic Driver Options +# +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_PM is not set +# CONFIG_PREEMPT is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="console=ttyS0,115200 mem=64M" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +# CONFIG_MTD_CFI_I2 is not set +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PNP2110=y +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_EDB7312 is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_NET_VENDOR_SMC=y +# CONFIG_SMC91X is not set +CONFIG_SMC91X_OLD=y +# CONFIG_SMC91X_OLD_TX_DMA is not set +# CONFIG_SMC91X_OLD_THROTTLE_TX is not set +# CONFIG_CIRRUS is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=m +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDE_TASKFILE_IO is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=m +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_FZKIDE=y +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set +# CONFIG_SERIO_I8042 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_SA1100_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_ISA is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_SCx200_ACB is not set +CONFIG_I2C_PXA=y + +# +# Hardware Sensors Chip support +# +CONFIG_I2C_SENSOR=y +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set + +# +# Other I2C Chip support +# +CONFIG_SENSORS_EEPROM=y +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_RTC8564 is not set +CONFIG_I2C_DEBUG_CORE=y +CONFIG_I2C_DEBUG_ALGO=y +CONFIG_I2C_DEBUG_BUS=y +CONFIG_I2C_DEBUG_CHIP=y + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +CONFIG_MINIX_FS=y +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_SYSFS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS_XATTR is not set +CONFIG_TMPFS=y +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# Misc devices +# + +# +# USB support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff -x .svn -urN linux-2.6.8-rc2/arch/arm/configs/trizeps2_defconfig linux-2.6.8-rc2-pnp1/arch/arm/configs/trizeps2_defconfig --- linux-2.6.8-rc2/arch/arm/configs/trizeps2_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/configs/trizeps2_defconfig 2004-07-27 13:59:09.000000000 +0200 @@ -0,0 +1,706 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +CONFIG_MMU=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_STANDALONE=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_IKCONFIG is not set +# CONFIG_EMBEDDED is not set +CONFIG_KALLSYMS=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# System Type +# +# CONFIG_ARCH_ADIFCC is not set +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP3XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set + +# +# CLPS711X/EP721X Implementations +# + +# +# Epxa10db +# + +# +# Footbridge Implementations +# + +# +# IOP3xx Implementation Options +# +# CONFIG_ARCH_IOP310 is not set +# CONFIG_ARCH_IOP321 is not set + +# +# IOP3xx Chipset Features +# + +# +# Intel PXA250/210 Implementations +# +# CONFIG_ARCH_CSB226 is not set +# CONFIG_ARCH_PXA_IDP is not set +CONFIG_ARCH_INNOKOM=y +# CONFIG_ARCH_LOGODL is not set +# CONFIG_ARCH_LUBBOCK is not set +CONFIG_ARCH_TRIZEPS2=y + +# +# SA11x0 Implementations +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_MINICACHE=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +CONFIG_XSCALE_PMU=y + +# +# General setup +# +# CONFIG_ZBOOT_ROM is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=y +CONFIG_PCMCIA_DEBUG=y +# CONFIG_TCIC is not set + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set +# CONFIG_PM is not set +# CONFIG_PREEMPT is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="root=/dev/nfs mem=32M ip=dhcp console=ttyS0,19200" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_INNOKOM=y +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_EDB7312 is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play support +# +CONFIG_PNP=y +CONFIG_PNP_DEBUG=y + +# +# Protocols +# +# CONFIG_ISAPNP is not set +# CONFIG_PNPBIOS is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_NETFILTER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_NET_SB1000 is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_SMC91X is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +CONFIG_NET_RADIO=y + +# +# Obsolete Wireless cards support (pre-802.11) +# +# CONFIG_STRIP is not set +# CONFIG_PCMCIA_WAVELAN is not set +# CONFIG_PCMCIA_NETWAVE is not set + +# +# Wireless 802.11 Frequency Hopping cards support +# +# CONFIG_PCMCIA_RAYCS is not set + +# +# Wireless 802.11b ISA/PCI cards support +# +CONFIG_HERMES=y + +# +# Wireless 802.11b Pcmcia/Cardbus cards support +# +CONFIG_PCMCIA_HERMES=y +# CONFIG_AIRO_CS is not set +# CONFIG_PCMCIA_ATMEL is not set +# CONFIG_PCMCIA_WL3501 is not set +CONFIG_NET_WIRELESS=y +# CONFIG_HOSTAP is not set + +# +# Token Ring devices +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +# CONFIG_NET_PCMCIA is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_TSLIBDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set +# CONFIG_SERIO_I8042 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_DZ is not set +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set + +# +# L3 serial bus support +# +# CONFIG_L3 is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_RAW_DRIVER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS=y +# CONFIG_DEVPTS_FS_XATTR is not set +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# +# CONFIG_MCP is not set + +# +# Console Switches +# +# CONFIG_SWITCHES is not set + +# +# USB support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff -x .svn -urN linux-2.6.8-rc2/arch/arm/Kconfig linux-2.6.8-rc2-pnp1/arch/arm/Kconfig --- linux-2.6.8-rc2/arch/arm/Kconfig 2004-07-27 14:08:03.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/Kconfig 2004-07-27 13:59:06.000000000 +0200 @@ -308,6 +308,8 @@ depends on FOOTBRIDGE_HOST || ARCH_SHARK default y +source "drivers/fpbus/Kconfig" + config FIQ bool depends on ARCH_ACORN || ARCH_L7200 || ARCH_LH7A400 diff -x .svn -urN linux-2.6.8-rc2/arch/arm/kernel/setup.c linux-2.6.8-rc2-pnp1/arch/arm/kernel/setup.c --- linux-2.6.8-rc2/arch/arm/kernel/setup.c 2004-07-27 14:08:03.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/kernel/setup.c 2004-07-27 13:59:06.000000000 +0200 @@ -683,8 +683,9 @@ struct tag *tags = (struct tag *)&init_tags; struct machine_desc *mdesc; char *from = default_command_line; - + setup_processor(); + mdesc = setup_machine(machine_arch_type); machine_name = mdesc->name; diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mach-pxa/csb226.c linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/csb226.c --- linux-2.6.8-rc2/arch/arm/mach-pxa/csb226.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/csb226.c 2004-07-27 13:59:10.000000000 +0200 @@ -0,0 +1,143 @@ +/* + * linux/arch/arm/mach-pxa/csb226.c + * + * (c) 2002, 2003 Robert Schwebel , Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "generic.h" + +#if 0 +#include +#include +#endif + +static void __init csb226_init_irq(void) +{ + pxa_init_irq(); + +} + +/* + * Ressource entries for onboard devices + */ + +static struct resource cs8900_resources[] = { + [0] = { + .start = CSB226_ETH_PHYS, + .end = CSB226_ETH_PHYS + CSB226_ETH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CSB226_ETH_IRQ, + .end = CSB226_ETH_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cs8900_device = { + .name = "cs8900", + .id = 0, + .num_resources = ARRAY_SIZE(cs8900_resources), + .resource = cs8900_resources, +}; + +static struct platform_device *devices[] __initdata = { + &cs8900_device, +}; + +static int __init csb226_init(void) +{ + /* add device entries */ + return platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +__initcall(csb226_init); + +#if 0 +// obsolete in 2.6...? [RSC] +static void __init +fixup_csb226(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ + /* we probably want to get this information from the bootloader later */ + SET_BANK (0, 0xa0000000, 64*1024*1024); + mi->nr_banks = 1; +} +#endif + +/* memory mapping */ +static struct map_desc csb226_io_desc[] __initdata = { + /* virtual physical length domain */ + { CSB226_ETH_VIRT, CSB226_ETH_PHYS, CSB226_ETH_SIZE, MT_DEVICE }, /* CS8900 LAN controller */ +}; + + +static void __init csb226_map_io(void) +{ + pxa_map_io(); + iotable_init(csb226_io_desc, ARRAY_SIZE(csb226_io_desc)); + + /* This enables the BTUART */ + CKEN |= CKEN7_BTUART; + pxa_gpio_mode(GPIO42_BTRXD_MD); + pxa_gpio_mode(GPIO43_BTTXD_MD); + pxa_gpio_mode(GPIO44_BTCTS_MD); + pxa_gpio_mode(GPIO45_BTRTS_MD); + + /* This is for the CS8900 chip select */ + pxa_gpio_mode(GPIO78_nCS_2_MD); + + /* setup sleep mode values */ + PWER = 0x00000002; + PFER = 0x00000000; + PRER = 0x00000002; + PGSR0 = 0x00008000; + PGSR1 = 0x003F0202; + PGSR2 = 0x0001C000; + PCFR |= PCFR_OPDE; +} + + +MACHINE_START(CSB226, "Cogent CSB226 Development Platform") + MAINTAINER("Robert Schwebel, Pengutronix") + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000)) + BOOT_PARAMS(0xa0000100) + MAPIO(csb226_map_io) + INITIRQ(csb226_init_irq) + INITTIME(pxa_init_time) +MACHINE_END diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mach-pxa/innokom.c linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/innokom.c --- linux-2.6.8-rc2/arch/arm/mach-pxa/innokom.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/innokom.c 2004-07-27 13:59:10.000000000 +0200 @@ -0,0 +1,206 @@ +/* + * linux/arch/arm/mach-pxa/innokom.c + * + * (c) 2004 Robert Schwebel , Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +//#include +#include + +#include "generic.h" + +/* + * Interrupt Handler for Software Update button + */ +static irqreturn_t sw_update_handler(int irq, void* dev_id,struct pt_regs* regs) +{ + printk("software update button pressed (I'm the dummy irq handler)\n"); + printk("USIR0 = %08x\n", USIR0); + printk("UDCCR = %08x\n", UDCCR); + printk("UDCCS0 = %08x\n", UDCCS0); + + return IRQ_HANDLED; +} + +/* + * Interrupt Handler for Reset button + */ +static irqreturn_t reset_handler(int irq, void* dev_id,struct pt_regs* regs) +{ + return IRQ_HANDLED; +} + + +/* + * Interrupt Initialisation + */ +static void __init innokom_init_irq(void) +{ + pxa_init_irq(); + + set_irq_type(INNOKOM_SW_UPDATE_IRQ, INNOKOM_SW_UPDATE_IRQ_EDGE); + set_irq_type(INNOKOM_RESET_IRQ, INNOKOM_RESET_IRQ_EDGE); + set_irq_type(INNOKOM_ETH_IRQ, INNOKOM_ETH_IRQ_EDGE); + set_irq_type(INNOKOM_USB_DISC_IRQ, INNOKOM_USB_DISC_IRQ_EDGE); +} + +/* + * Ressource entries for onboard devices + */ + +static struct resource smc91x_resources[] = { + [0] = { + .start = INNOKOM_ETH_PHYS, + .end = INNOKOM_ETH_PHYS + INNOKOM_ETH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INNOKOM_ETH_IRQ, + .end = INNOKOM_ETH_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct resource innokom_switches_resources[] = { + [0] = { + .start = INNOKOM_SW_UPDATE_IRQ, + .end = INNOKOM_SW_UPDATE_IRQ, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = INNOKOM_RESET_IRQ, + .end = INNOKOM_RESET_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device innokom_switches_device = { + .name = "innokom switches", + .id = 1, + .num_resources = ARRAY_SIZE(innokom_switches_resources), + .resource = innokom_switches_resources, +}; + +static struct platform_device *devices[] __initdata = { + &smc91x_device, + &innokom_switches_device, +}; + +/* + * Specific Board Initialisation + */ +static int __init innokom_init(void) +{ + /* init innokom irqs */ + + /* reset button */ + if (request_irq(INNOKOM_RESET_IRQ, &reset_handler, 0, "reset button", NULL)) + printk(KERN_INFO "innokom: can't get assigned irq %i\n (reset button)",INNOKOM_RESET_IRQ); + else + set_irq_type(INNOKOM_RESET_IRQ, INNOKOM_RESET_IRQ_EDGE); + + /* sw update button */ + if (request_irq(INNOKOM_SW_UPDATE_IRQ, &sw_update_handler, 0, "software update button", NULL)) + printk(KERN_INFO "innokom: can't get assigned irq %i (sw update button)\n", INNOKOM_SW_UPDATE_IRQ); + else + set_irq_type(INNOKOM_SW_UPDATE_IRQ, INNOKOM_SW_UPDATE_IRQ_EDGE); + + /* smc91111 ethernet irq */ +// set_irq_type(INNOKOM_ETH_IRQ, INNOKOM_ETH_IRQ_EDGE); + + /* USB disconnect irq */ +// set_irq_type(INNOKOM_USB_DISC_IRQ, INNOKOM_USB_DISC_IRQ_EDGE); + + /* add device entries */ + return platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +subsys_initcall(innokom_init); + +/* memory mapping */ +static struct map_desc innokom_io_desc[] __initdata = { +/* virtual physical length type */ + { INNOKOM_ETH_VIRT, INNOKOM_ETH_PHYS, INNOKOM_ETH_SIZE, MT_DEVICE }, /* ETH SMSC 91111 */ +}; + +static void __init innokom_map_io(void) +{ + pxa_map_io(); + iotable_init(innokom_io_desc, ARRAY_SIZE(innokom_io_desc)); + + /* Enable the BTUART */ + CKEN |= CKEN7_BTUART; + pxa_gpio_mode(GPIO42_BTRXD_MD); + pxa_gpio_mode(GPIO43_BTTXD_MD); + pxa_gpio_mode(GPIO44_BTCTS_MD); + pxa_gpio_mode(GPIO45_BTRTS_MD); + + pxa_gpio_mode(GPIO33_nCS_5_MD); /* SMSC network chip */ + + /* setup sleep mode values */ + PWER = 0x00000002; + PFER = 0x00000000; + PRER = 0x00000002; + PGSR0 = 0x00008000; + PGSR1 = 0x003F0202; + PGSR2 = 0x0001C000; + PCFR |= PCFR_OPDE; +} + +/* FIXME: memory tags should be set correctly */ +static void __init innokom_fixup(struct machine_desc *desc, + struct tag *tag, + char **cmdline, struct meminfo *mi) +{ + SET_BANK(0, 0xa0000000, (64*1024*1024)); + mi->nr_banks = 1; +} + +MACHINE_START(INNOKOM, "Auerswald Innokom") + MAINTAINER("Robert Schwebel, Pengutronix") + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000)) + BOOT_PARAMS(0xa0000100) + FIXUP(innokom_fixup) + MAPIO(innokom_map_io) + INITIRQ(innokom_init_irq) + INITTIME(pxa_init_time) +MACHINE_END diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mach-pxa/Kconfig linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/Kconfig --- linux-2.6.8-rc2/arch/arm/mach-pxa/Kconfig 2004-06-16 07:19:02.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/Kconfig 2004-07-27 13:59:10.000000000 +0200 @@ -5,6 +5,18 @@ choice prompt "Select target board" +config ARCH_CSB226 + bool "Cogent CSB226" + select PXA25x + +config ARCH_INNOKOM + bool "Auerswald Innokom" + select PXA25x + +config ARCH_LOGODL + bool "Logotronic LogoDL" + select PXA25x + config ARCH_LUBBOCK bool "Intel DBPXA250 Development Platform" select PXA25x @@ -14,10 +26,18 @@ select PXA27x #select IWMMXT +config ARCH_PXA_PNP2110 + bool "SSV PNP/2110-3V Platform" + select PXA25x + config ARCH_PXA_IDP bool "Accelent Xscale IDP" select PXA25x +config ARCH_TRIZEPS2 + bool "Keith & Koep Trizeps2" + select PXA25x + endchoice endmenu diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mach-pxa/leds-logodl.c linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/leds-logodl.c --- linux-2.6.8-rc2/arch/arm/mach-pxa/leds-logodl.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/leds-logodl.c 2004-07-27 13:59:10.000000000 +0200 @@ -0,0 +1,135 @@ +/* + * (C) 2002 Abraham van der Merwe + * (C) 2003 August Hoerandl , Logotronic GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include +#include + +#include "leds.h" + +#define CFG_LED_A_BIT (1<<18) +#define CFG_LED_A_SR GPSR0 +#define CFG_LED_A_CR GPCR0 + +#define CFG_LED_B_BIT (1<<16) +#define CFG_LED_B_SR GPSR1 +#define CFG_LED_B_CR GPCR1 + +static int status_led6 = 0; +static int status_led7 = 0; + +static void led6_on(void) { CFG_LED_A_CR = CFG_LED_A_BIT; status_led6 = 1; } +static void led6_off(void) { CFG_LED_A_SR = CFG_LED_A_BIT; status_led6 = 0; } +static void led6_invert(void) +{ + if (status_led6) + led6_off(); + else + led6_on(); +} + +#define led7_on() { CFG_LED_B_CR = CFG_LED_B_BIT; status_led7 = 1; } +#define led7_off() { CFG_LED_B_SR = CFG_LED_B_BIT; status_led7 = 1; } + + +static int claimed; + +void logodl_leds_event (led_event_t evt) +{ + unsigned long flags; + + local_irq_save (flags); + + switch (evt) + { +#ifdef CONFIG_LEDS_CPU + /* turn off CPU load LED */ + case led_idle_start: + if (!claimed) led7_off (); + break; + + /* turn on CPU load LED */ + case led_idle_end: + if (!claimed) led7_on (); + break; +#endif + +#ifdef CONFIG_LEDS_TIMER + /* toggle heartbeat LED */ + case led_timer: + if (!claimed) led6_invert (); + break; +#endif + + /* start: turn on LEDs and set claimed to 0 */ + case led_start: + led6_on (); + led7_on (); + claimed = 0; + break; + + /* stop: turn off LEDs */ + case led_stop: + led6_off (); + led7_off (); + break; + + /* override CPU load & timer LEDs */ + case led_claim: + claimed = 1; + break; + + /* restore CPU load & timer LEDs */ + case led_release: + claimed = 0; + break; + + /* direct LED access (must be previously claimed) */ + + /* led7 */ + case led_green_on: + if (claimed) led7_on (); + break; + + case led_green_off: + if (claimed) led7_off (); + break; + + /* led6 -- at the moment this is actually also green */ + case led_red_on: + if (claimed) led6_on (); + break; + + case led_red_off: + if (claimed) led6_off (); + break; + + default: + break; + } + + local_irq_restore (flags); +} diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mach-pxa/logodl.c linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/logodl.c --- linux-2.6.8-rc2/arch/arm/mach-pxa/logodl.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/logodl.c 2004-07-27 13:59:10.000000000 +0200 @@ -0,0 +1,95 @@ +/* + * (C) 2002 Abraham van der Merwe + * (C) 2003 August Hoerandl , Logotronic GmbH + * (C) 2003 Robert Schwebel , Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "generic.h" + +#define CFG_LED_A_BIT (1<<18) +#define CFG_LED_A_SR GPSR0 +#define CFG_LED_A_CR GPCR0 + +#define CFG_LED_B_BIT (1<<16) +#define CFG_LED_B_SR GPSR1 +#define CFG_LED_B_CR GPCR1 + +static int __init logodl_init(void) +{ + return 0; +} + +__initcall(logodl_init); + +static void __init +logodl_fixup(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ + /* we probably want to get this information from the bootloader later */ + SET_BANK (0, 0x08000000, 4*1024*1024); + mi->nr_banks = 1; +} + +static void __init logodl_init_irq(void) +{ + pxa_init_irq(); +} + +static struct map_desc logodl_io_desc[] __initdata = { + /* virtual physical length type */ + {LOGODL_UART_VIRT, LOGODL_UART_PHYS, LOGODL_UART_SIZE, 0, 1, 0, 0 }, + {LOGODL_USB_VIRT, LOGODL_USB_PHYS, LOGODL_USB_SIZE, 0, 1, 0, 0 }, + {LOGODL_ETH_VIRT, LOGODL_ETH_PHYS, LOGODL_ETH_SIZE, 0, 1, 0, 0 }, + {LOGODL_CPLD_VIRT, LOGODL_CPLD_PHYS, LOGODL_CPLD_SIZE, 0, 1, 0, 0 }, + LAST_DESC +}; + +static void __init logodl_map_io(void) +{ + pxa_map_io(); + iotable_init(logodl_io_desc); +} + + +MACHINE_START(LOGODL, "Logotronic DL") + MAINTAINER("August Hoerandl, Logotronic; Robert Schwebel, Pengutronix") + BOOT_MEM(0x08000000, 0x40000000, io_p2v(0x40000000)) + BOOT_PARAMS(0x08000100) + FIXUP(logodl_fixup) + MAPIO(logodl_map_io) + INITIRQ(logodl_init_irq) + INITTIME(pxa_init_time) +MACHINE_END diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mach-pxa/Makefile linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/Makefile --- linux-2.6.8-rc2/arch/arm/mach-pxa/Makefile 2004-07-27 14:08:03.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/Makefile 2004-07-27 13:59:10.000000000 +0200 @@ -8,12 +8,18 @@ obj-$(CONFIG_PXA27x) += pxa27x.o # Specific board support +obj-$(CONFIG_ARCH_CSB226) += csb226.o +obj-$(CONFIG_ARCH_INNOKOM) += innokom.o +obj-$(CONFIG_ARCH_LOGODL) += logodl.o obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o +obj-$(CONFIG_ARCH_PXA_PNP2110) += pnp2110.o obj-$(CONFIG_ARCH_PXA_IDP) += idp.o +obj-$(CONFIG_ARCH_TRIZEPS2)+= trizeps2.o # Support for blinky lights led-y := leds.o +led-$(CONFIG_ARCH_LOGODL) += leds-logodl.o led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mach-pxa/pnp2110.c linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/pnp2110.c --- linux-2.6.8-rc2/arch/arm/mach-pxa/pnp2110.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/pnp2110.c 2004-07-27 13:59:10.000000000 +0200 @@ -0,0 +1,191 @@ +/* + * linux/arch/arm/mach-pxa/pnp2110.c + * + * (C) 2003 SSV Marco Hasewinkel, Embedded Systems + * (C) 2004 Pengutronix, Robert Schwebel + * + * Support for the SSV PNP/2110-3V Platform. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include "generic.h" + +/* + * FIXME: RSC: + * + * - fix memory tag in bootloader + * + * - direction for GPIOs: + * set_GPIO_IRQ_edge(1 ,GPIO_RISING_EDGE); GPIO1 = EXT IRQ + * + */ + +/* + * Interrupt Initialisation + */ +static void __init pnp2110_init_irq(void) +{ + pxa_init_irq(); + /* put into ressource!!! */ + set_irq_type(PNP2110_ETH_IRQ, PNP2110_ETH_IRQ_EDGE); +} + +/* + * Ressource entries for onboard devices + */ +static struct resource smc91x_resources[2]; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *devices[] __initdata = { + &smc91x_device, +}; + +/* + * Specific Board Initialisation + */ +static int __init pnp2110_init(void) +{ + u32 *smsc; + + /* + * Probe for SMSC network chips: different board revisions + * of the PNP2110 have different locations and parameters. We + * probe it here and let the driver use the ressources. + * + * FIXME: invent a command line based mechanism for that... [RSC] + */ + + memset(smc91x_resources,0,sizeof(smc91x_resources)); + + smsc = ioremap(0x04000300, 16); + if (smsc) { + if (((*(smsc+0x3)) & 0xFF000000) == 0x33000000) { + smc91x_resources[0].start = 0x04000300; + smc91x_resources[0].end = 0x0400030F; + smc91x_resources[0].flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT; + smc91x_resources[1].start = IRQ_GPIO(0); + smc91x_resources[1].end = IRQ_GPIO(0); + smc91x_resources[1].flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE; + printk("found smc91x in 32bit mode\n"); + iounmap(smsc); + goto found; + } + iounmap(smsc); + } + smsc = ioremap(0x2C000300, 16); + if (smsc) { + if (((*(smsc+0x3)) & 0xFF000000) == 0x33000000) { + smc91x_resources[0].start = 0x2C000300; + smc91x_resources[0].end = 0x2C00030F; + smc91x_resources[0].flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT; + smc91x_resources[1].start = IRQ_GPIO(0); + smc91x_resources[1].end = IRQ_GPIO(0); + smc91x_resources[1].flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE; + printk("found smc91x in 16bit mode\n"); + } + iounmap(smsc); + } +found: + return platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +subsys_initcall(pnp2110_init); + +#if 0 +static struct map_desc pnp2110_io_desc[] __initdata = { +/* virtual physical length type */ + { PNP2110_ETH_VIRT, PNP2110_ETH_PHYS, PNP2110_ETH_SIZE, MT_DEVICE }, /* ETH SMSC 91111 */ +}; +#endif + +static void __init pnp2110_map_io(void) +{ + pxa_map_io(); +// iotable_init(pnp2110_io_desc, ARRAY_SIZE(pnp2110_io_desc)); + + /* Enable the BTUART */ + CKEN |= CKEN7_BTUART; + pxa_gpio_mode(GPIO42_BTRXD_MD); + pxa_gpio_mode(GPIO43_BTTXD_MD); + pxa_gpio_mode(GPIO44_BTCTS_MD); + pxa_gpio_mode(GPIO45_BTRTS_MD); + +// pxa_gpio_mode(GPIO33_nCS_5_MD); /* SMSC network chip */ + + /* setup sleep mode values */ + PWER = 0x00000002; + PFER = 0x00000000; + PRER = 0x00000002; + PGSR0 = 0x00008000; + PGSR1 = 0x003F0202; + PGSR2 = 0x0001C000; + PCFR |= PCFR_OPDE; + + /* PCMCIA Socket 0 Timing - SSV has the ethernet chip located there */ + /* FIXME: put this into boot loader */ + MCMEM0 = 0x00000000; + MECR = 0x00000003; +} + +static void __init +pnp2110_fixup(struct machine_desc *desc, + struct tag *tag, + char **cmdline, struct meminfo *mi) +{ + /* FIXME: put this into bootloader */ + SET_BANK(0, 0xa0000000, (64*1024*1024)); + mi->nr_banks = 1; + +} + +MACHINE_START(PNP2110, "SSV PNP/2110-3V Platform") + MAINTAINER("Robert Schwebel, Pengutronix") + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000)) + BOOT_PARAMS(0xa0000100) + FIXUP(pnp2110_fixup) + MAPIO(pnp2110_map_io) + INITIRQ(pnp2110_init_irq) + INITTIME(pxa_init_time) +MACHINE_END + diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mach-pxa/trizeps2.c linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/trizeps2.c --- linux-2.6.8-rc2/arch/arm/mach-pxa/trizeps2.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/arch/arm/mach-pxa/trizeps2.c 2004-07-27 13:59:10.000000000 +0200 @@ -0,0 +1,107 @@ +/* + * linux/arch/arm/mach-pxa/trizeps2.c + * + * (c) 2004 Robert Schwebel , Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +//#include +#include + +#include "generic.h" + +/* + * Interrupt Initialisation + */ +static void __init trizeps2_init_irq(void) +{ + pxa_init_irq(); + +} + +static struct platform_device *devices[] __initdata = { +}; + +/* + * Specific Board Initialisation + */ +static int __init trizeps2_init(void) +{ + char buf[255]; + + sprintf(buf,"trizeps2_init\n"); printascii(buf); + return platform_add_devices(devices, ARRAY_SIZE(devices)); +} + + +subsys_initcall(trizeps2_init); + +/* memory mapping */ +static struct map_desc trizeps2_io_desc[] __initdata = { +/* virtual physical length type */ +// { INNOKOM_ETH_VIRT, INNOKOM_ETH_PHYS, INNOKOM_ETH_SIZE, MT_DEVICE }, /* ETH SMSC 91111 */ +}; + +static void __init trizeps2_map_io(void) +{ + pxa_map_io(); + //iotable_init(trizeps2_io_desc, ARRAY_SIZE(trizeps2_io_desc)); + + /* Enable the BTUART */ + CKEN |= CKEN7_BTUART; + pxa_gpio_mode(GPIO42_BTRXD_MD); + pxa_gpio_mode(GPIO43_BTTXD_MD); + pxa_gpio_mode(GPIO44_BTCTS_MD); + pxa_gpio_mode(GPIO45_BTRTS_MD); + + //pxa_gpio_mode(GPIO33_nCS_5_MD); /* SMSC network chip */ + + /* setup sleep mode values */ + PWER = 0x00000002; + PFER = 0x00000000; + PRER = 0x00000002; + PGSR0 = 0x00008000; + PGSR1 = 0x003F0202; + PGSR2 = 0x0001C000; + PCFR |= PCFR_OPDE; +} + +MACHINE_START(TRIZEPS2, "Keith & Koep Trizeps2") + MAINTAINER("Robert Schwebel, Pengutronix") + BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000)) + BOOT_PARAMS(0xa0000100) + MAPIO(trizeps2_map_io) + INITIRQ(trizeps2_init_irq) + INITTIME(pxa_init_time) +MACHINE_END diff -x .svn -urN linux-2.6.8-rc2/arch/arm/Makefile linux-2.6.8-rc2-pnp1/arch/arm/Makefile --- linux-2.6.8-rc2/arch/arm/Makefile 2004-07-27 14:08:03.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/Makefile 2004-07-27 13:59:08.000000000 +0200 @@ -51,12 +51,15 @@ tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 -tune-$(CONFIG_CPU_XSCALE) :=$(call check_gcc,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale +#tune-$(CONFIG_CPU_XSCALE) :=$(call check_gcc,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale +tune-$(CONFIG_CPU_XSCALE) :=-mtune=xscale -Wa,-mcpu=xscale tune-$(CONFIG_CPU_V6) :=-mtune=strongarm # Need -Uarm for gcc < 3.x -CFLAGS +=-mapcs-32 $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float -Wa,-mno-fpu -Uarm -AFLAGS +=-mapcs-32 $(arch-y) $(tune-y) -msoft-float -Wa,-mno-fpu +#CFLAGS +=-mapcs-32 $(arch-y) $(tune-y) -malignment-traps -msoft-float -Wa,-mno-fpu -Uarm +CFLAGS +=-mapcs-32 $(arch-y) $(tune-y) -malignment-traps -msoft-float -Uarm +#AFLAGS +=-mapcs-32 $(arch-y) $(tune-y) -msoft-float -Wa,-mno-fpu +AFLAGS +=-mapcs-32 $(arch-y) $(tune-y) -msoft-float #Default value DATAADDR := . diff -x .svn -urN linux-2.6.8-rc2/arch/arm/mm/alignment.c linux-2.6.8-rc2-pnp1/arch/arm/mm/alignment.c --- linux-2.6.8-rc2/arch/arm/mm/alignment.c 2004-06-16 07:18:59.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/mm/alignment.c 2004-07-27 13:59:10.000000000 +0200 @@ -449,7 +449,7 @@ return TYPE_ERROR; } -static int +int do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { union offset_union offset; diff -x .svn -urN linux-2.6.8-rc2/arch/arm/oprofile/op_model_xscale.c linux-2.6.8-rc2-pnp1/arch/arm/oprofile/op_model_xscale.c --- linux-2.6.8-rc2/arch/arm/oprofile/op_model_xscale.c 2004-06-16 07:19:31.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/arch/arm/oprofile/op_model_xscale.c 2004-07-27 13:59:06.000000000 +0200 @@ -41,7 +41,9 @@ #ifdef CONFIG_ARCH_IOP331 #define XSCALE_PMU_IRQ IRQ_IOP331_CORE_PMU #endif - +#ifdef CONFIG_ARCH_PXA +#define XSCALE_PMU_IRQ IRQ_PMU +#endif /* * Different types of events that can be counted by the XScale PMU * as used by Oprofile userspace. Here primarily for documentation diff -x .svn -urN linux-2.6.8-rc2/CHANGELOG.ptx linux-2.6.8-rc2-pnp1/CHANGELOG.ptx --- linux-2.6.8-rc2/CHANGELOG.ptx 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/CHANGELOG.ptx 2004-07-27 13:58:19.000000000 +0200 @@ -0,0 +1,25 @@ +2004-06-30 Robert Schwebel + + - fixed compiler options for gcc 3.4 (short-load-bytes) + - released 2.6.7-mtd20040622-ptx4 + +2004-06-29 Robert Schwebel + + - fixed MTD, it works again now + - released 2.6.7-mtd20040622-ptx3 + +2004-06-27 Robert Schwebel + + - MTD problem still needs fixing (some memory + was not set to 0 after being allocated) + - Fixed network driver for PNP2110 + +2004-06-24 Robert Schwebel + + - ported 2.6.0-rmk2-ptx1 to 2.6.7 + - added 20040622 MTD snapshot release + - we still see strange effects which lets us not + mount JFFS2 partitions from the old innokom + correctly + - in 2.4, 2.4.26-vrs2-pxa1-ptx4 has our current + stuff. This has to be ported to this release. diff -x .svn -urN linux-2.6.8-rc2/drivers/base/platform.c linux-2.6.8-rc2-pnp1/drivers/base/platform.c --- linux-2.6.8-rc2/drivers/base/platform.c 2004-07-27 14:08:04.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/base/platform.c 2004-07-27 14:02:43.000000000 +0200 @@ -308,3 +308,5 @@ EXPORT_SYMBOL(platform_device_unregister); EXPORT_SYMBOL(platform_get_irq); EXPORT_SYMBOL(platform_get_resource); +EXPORT_SYMBOL(platform_add_devices); + diff -x .svn -urN linux-2.6.8-rc2/drivers/fpbus/fpbus.c linux-2.6.8-rc2-pnp1/drivers/fpbus/fpbus.c --- linux-2.6.8-rc2/drivers/fpbus/fpbus.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/fpbus/fpbus.c 2004-07-27 14:00:18.000000000 +0200 @@ -0,0 +1,268 @@ +/* + * fpbus.c + * + * (c) 2004 by Robert Schwebel, Pengutronix + * + * This driver provides the base infrastructure for in-FPGA + * devices. + * + */ + +#include +#include +#include +#include +#include +#include + +#define DEBUG 1 + +#define DRIVER_NAME "fpbus" +#define DRIVER_VERS "00000000" +static const char firmware_file[] = DRIVER_NAME"-"DRIVER_VERS".rbf"; + +static struct platform_device fpbus_device; +static struct resource fpbus_resource[]; +static struct bus_type fpbus_bus_type; + +static int fpbus_probe(union ftag *tag); + +/* Dummy tagged list, until we have a real one ---------------------------- */ + +union ftag config_space[] = { + + {.core = { + .tag_type = FTAG_CORE, + .firmware_revision[0] = 0x00010203, + .firmware_revision[1] = 0x04050607, + .firmware_revision[2] = 0x08090a0b, + .firmware_revision[3] = 0x0c0d0e0f, + .version_number = 0x00000001, + .compile_date = 0x00000000, + .timing_cs3 = 0x00000000, + .timing_cs4 = 0x00000000, + }}, + {.dev = { + .tag_type = FTAG_DEV, + .dev_id = 0x00000000, + .dev_sub_id = 0x00000000, + .interface_revision = 0x0000, + .ip_revision = 0x0000, + .base_address = 0x00000000, + .size = 0x00000000, + }}, + {.end = { + .tag_type = FTAG_END, + }}, +}; + +/* + * chip driver registration functions + */ + +static struct fpbus_ops *chip_driver_ops = NULL; + +int fpbus_register(struct fpbus_ops *ops) +{ + const struct firmware *fw_entry = 0; + union ftag *tagged_list; + int ret; + + if (!ops) return + -EINVAL; + + if (chip_driver_ops) + return -EBUSY; + + chip_driver_ops = ops; + + /* request firmware */ + printk("%s: requesting firmware (%s)\n", DRIVER_NAME, + firmware_file); + if ((ret = request_firmware(&fw_entry, firmware_file, &fpbus_device.dev))) { + printk(KERN_ERR "could not load firmware (error=%i) - exiting.\n", ret); + return ret; + }; + + printk("%s: loading firmware into FPGA\n", DRIVER_NAME); + if (ops->fpbus_init_device(fw_entry)) { + printk("%s: loading firmware failed!\n", DRIVER_NAME); + release_firmware(fw_entry); + chip_driver_ops = NULL; + return -EIO; + } + + /* probe for devices */ + //tagged_list = ioremap(PII_FPGA1_VIRT, PII_FPGA1_SIZE); + tagged_list = (union ftag *) config_space; + + if (!fpbus_probe(tagged_list)) { + printk(KERN_ERR + "illegal tag found in PII_FPGA configuration space - exiting.\n"); + release_firmware(fw_entry); + return -ENODEV; + } + return 0; +} + +void fpbus_unregister(struct fpbus_ops *ops) +{ + if (chip_driver_ops) + chip_driver_ops = NULL; + return; +} + +/** + * fpbus_match - tell if a fpbus device structure has matching device id + * + * @dev: + * @drv: + * Used by a driver to check whether another PII_FPGA device present in the + * system is in its list of supported devices.Returns the matching + * pii_device_id structure or %NULL if there is no match. + * + */ +static int +fpbus_match(struct device *dev, struct device_driver *drv) +{ + return 1; +} + +/** + * + * + */ +#if CONFIG_HOTPLUG +int +fpbus_hotplug(struct device *dev, char **envp, int num_envp, + char *buffer, int buffer_size) +{ + if (!dev) + return -ENODEV; + + return -ENODEV; +} +#endif + +/** + * + * + */ +static int +fpbus_suspend(struct device *dev, u32 state) +{ + printk("%s: suspending\n", DRIVER_NAME); + return 0; +} + +/** + * + * + */ +static int +fpbus_resume(struct device *dev) +{ + printk("%s: resuming\n", DRIVER_NAME); + return 0; +} + +/** + * fpbus_probe - parse tagged list and probe for devices + * + * @fpga_base: where to start searching for tagged list + * + * returns 0 in case of an error, 1 otherwhise. + */ +static int +fpbus_probe(union ftag *tag) +{ + printk(KERN_INFO "probing PII_FPGA for tagged list:\n"); + + do { + switch ((*tag).tag.tag_type) { + case FTAG_CORE: + printk(KERN_INFO "start of list\n"); + (struct ftag_core *) tag++; + break; + case FTAG_DEV: + printk(KERN_INFO "device:\n"); + (struct ftag_dev *) tag++; + break; + default: + return 0; + } + + } while ((*tag).tag.tag_type != FTAG_END); + + printk(KERN_INFO "end of list\n"); + + return 1; +} + +static void +fpbus_device_release(struct device *dev) +{ + printk(KERN_WARNING "%s: uggly hack: this should be taks of the platform device framework\n", DRIVER_NAME); +}; + +static struct bus_type fpbus_bus_type = { + .name = "fpbus", + .match = fpbus_match, + .hotplug = fpbus_hotplug, + .suspend = fpbus_suspend, + .resume = fpbus_resume +}; + +static struct resource fpbus_resource[] = { + { + .start = 0x00000000, + .end = 0x00000000, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device fpbus_device = { + .name = "fpbus", + .id = 0, + .num_resources = ARRAY_SIZE(fpbus_resource), + .resource = fpbus_resource, + .dev = { + .release = fpbus_device_release, /* FIXME: should be job of platform code */ + }, +}; + +static int fpbus_driver_init(void) +{ + printk("%s: registering fpbus_device\n", DRIVER_NAME); + if (platform_device_register(&fpbus_device)) { + printk(KERN_ERR "%s: could not register device\n", DRIVER_NAME); + return -ENOENT; + }; + + /* we register our own bus type */ + if (bus_register(&fpbus_bus_type)) { + printk(KERN_ERR "%s: could not register bus\n", DRIVER_NAME); + platform_device_unregister(&fpbus_device); + return -ENODEV; + } + + return 0; +} + +static void +fpbus_driver_exit(void) +{ + bus_unregister(&fpbus_bus_type); + platform_device_unregister(&fpbus_device); +} + +module_init(fpbus_driver_init); +module_exit(fpbus_driver_exit); + +EXPORT_SYMBOL(fpbus_match); +EXPORT_SYMBOL(fpbus_hotplug); +EXPORT_SYMBOL(fpbus_suspend); +EXPORT_SYMBOL(fpbus_resume); +EXPORT_SYMBOL(fpbus_register); +EXPORT_SYMBOL(fpbus_unregister); + diff -x .svn -urN linux-2.6.8-rc2/drivers/fpbus/fpbus-tb2.c linux-2.6.8-rc2-pnp1/drivers/fpbus/fpbus-tb2.c --- linux-2.6.8-rc2/drivers/fpbus/fpbus-tb2.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/fpbus/fpbus-tb2.c 2004-07-27 14:00:18.000000000 +0200 @@ -0,0 +1,157 @@ +/* + * drivers/fpbus/fpbus.c + * + * (c) 2004 by Robert Schwebel, Pengutronix + * + * This is a chip driver for the fpbus on NGE TB1. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DEBUG 1 + +#define DRIVER_NAME "fpbus-tb2" + +/* + * This is our hardware connection + */ +#undef FPBUS_MSEL0 +#undef FPBUS_MSEL1 +#define FPBUS_DATA0 58 +#define FPBUS_DCLK 59 +#define FPBUS_CONF_DONE 61 +#define FPBUS_NCONFIG 62 +#define FPBUS_NSTATUS 60 + +static int init_finished = 0; + +/** + * fpbus_tb2_init_device - push the firmware into the device + * + * @fw: firmware to be flashed into the device + */ +int fpbus_tb2_init_device(const struct firmware *fw) +{ + int timeout; + int bits_transferred = 0; + int ret; + u8 *buf = fw->data; + size_t size = fw->size; + + printk(KERN_INFO "%s: transferring %i bytes into FPGA\n", fw->size); + + /* request gpio pins and initialize */ + ret = request_gpio(FPBUS_NCONFIG, DRIVER_NAME, GPIO_KERNEL|GPIO_OUTPUT, 0); + if (ret) goto err_nconfig; + ret = request_gpio(FPBUS_DATA0, DRIVER_NAME, GPIO_KERNEL|GPIO_OUTPUT, 0); + if (ret) goto err_data0; + ret = request_gpio(FPBUS_DCLK, DRIVER_NAME, GPIO_KERNEL|GPIO_OUTPUT, 0); + if (ret) goto err_dclk; + ret = request_gpio(FPBUS_NSTATUS, DRIVER_NAME, GPIO_KERNEL|GPIO_INPUT, 0); + if (ret) goto err_nstatus; + ret = request_gpio(FPBUS_CONF_DONE, DRIVER_NAME, GPIO_KERNEL|GPIO_INPUT, 0); + if (ret) goto err_conf_done; + + /* positive edge after > 40 us low time initiates data transfer */ + udelay(50); + gpio_set_pin(FPBUS_NCONFIG); + + /* positive edge on nSTATUS indicates that device is ready */ + timeout=50; + while (!gpio_get_pin(FPBUS_NSTATUS) && (timeout--)) + udelay(1); + + if (timeout==0) + return -ENODEV; + + /* wait > 1 us until transfer starts */ + udelay(2); + + while (!gpio_get_pin(FPBUS_CONF_DONE)) { + + if (*buf & 0x1) + gpio_set_pin(FPBUS_DATA0); + else + gpio_clear_pin(FPBUS_DATA0); + + udelay(1); /* FIXME: > 7 ns */ + gpio_set_pin(FPBUS_DCLK); /* valid on positive edge */ + udelay(1); /* FIXME: > 4 ns */ + gpio_clear_pin(FPBUS_DCLK); + *buf >>= 1; + if (!(++bits_transferred % 8)) { + buf++; + printk("."); + } + if ((bits_transferred / 8) > size) + break; + } + + /* + * we are either finished or have tried to tranfer more than + * size bytes + */ + + if (!gpio_get_pin(FPBUS_CONF_DONE)) { + printk(KERN_ERR "%s: device didn't finish configuation " + "after firmware was transferred\n", DRIVER_NAME); + return -ENODEV; + } + + init_finished = 1; + + return 0; + +err_nstatus: + free_gpio(FPBUS_NSTATUS); +err_conf_done: + free_gpio(FPBUS_CONF_DONE); +err_dclk: + free_gpio(FPBUS_DCLK); +err_data0: + free_gpio(FPBUS_DATA0); +err_nconfig: + free_gpio(FPBUS_NCONFIG); + printk(KERN_ERR "%s: error requesting GPIO pins\n", DRIVER_NAME); + return -ENOMEM; +} + +static struct fpbus_ops fpbus_tb2_ops = { + .fpbus_init_device = fpbus_tb2_init_device, +}; + +static int fpbus_tb2_init(void) +{ + return fpbus_register(&fpbus_tb2_ops); +} + +/** + * FIXME: don't leave FPGA pins as floating inputs when finished... + */ +static void fpbus_tb2_exit(void) +{ + fpbus_unregister(&fpbus_tb2_ops); + if (init_finished) { + free_gpio(FPBUS_NCONFIG); + free_gpio(FPBUS_DATA0); + free_gpio(FPBUS_DCLK); + free_gpio(FPBUS_NSTATUS); + free_gpio(FPBUS_CONF_DONE); + } + return; +} + +module_init(fpbus_tb2_init); +module_exit(fpbus_tb2_exit); + +MODULE_LICENSE("GPL"); + diff -x .svn -urN linux-2.6.8-rc2/drivers/fpbus/Kconfig linux-2.6.8-rc2-pnp1/drivers/fpbus/Kconfig --- linux-2.6.8-rc2/drivers/fpbus/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/fpbus/Kconfig 2004-07-27 14:00:18.000000000 +0200 @@ -0,0 +1,29 @@ +# +# fpbus configuration +# + +config FPBUS + bool "fpbus" + default n + help + This is a bus driver for in-FPGA devices. It can be + autoprobed. + + FIXME: More documentation has to be written. + + If you don't know what to do here, say N. + +config FPBUS_NGE + bool "NGE platforms" + depends on FPBUS + default n + help + This enables fpbus support on NGE platforms (PNP2110 based). + +config FPBUS_NGE_TB2 + tristate "Testboard2" + depends on FPBUS_NGE + default n + help + This enables fpbus support for NGE testboard 2 (PNP2110 based). + diff -x .svn -urN linux-2.6.8-rc2/drivers/fpbus/Makefile linux-2.6.8-rc2-pnp1/drivers/fpbus/Makefile --- linux-2.6.8-rc2/drivers/fpbus/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/fpbus/Makefile 2004-07-27 14:00:18.000000000 +0200 @@ -0,0 +1,7 @@ +# +# Makefile for the fpbus specific drivers. +# + +obj-$(CONFIG_FPBUS) += fpbus.o +obj-$(CONFIG_FPBUS_NGE_TB2) += fpbus-tb2.o + diff -x .svn -urN linux-2.6.8-rc2/drivers/i2c/algos/i2c-algo-pxa.c linux-2.6.8-rc2-pnp1/drivers/i2c/algos/i2c-algo-pxa.c --- linux-2.6.8-rc2/drivers/i2c/algos/i2c-algo-pxa.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/i2c/algos/i2c-algo-pxa.c 2004-07-27 14:02:47.000000000 +0200 @@ -0,0 +1,343 @@ +/* + * i2c-algo-pxa.c + * + * I2C algorithm for the PXA I2C bus access. + * Byte driven algorithm similar to pcf. + * + * Copyright (C) 2002 Intrinsyc Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History: + * Apr 2002: Initial version [CS] + * Jun 2002: Properly seperated algo/adap [FB] + * Jan 2003: added limited signal handling [Kai-Uwe Bloem] + * Jan 2003: allow SMBUS_QUICK as valid msg [FB] + * Jun 2003: updated for 2.5 [Dustin McIntire] + * ...: more updates for 2.6 [Holger Schurig] + * + */ +#include +#include + +#include +#include +#include +#include /* struct i2c_msg and others */ +#include + +#include + +/* + * Set this to zero to remove all the debug statements via dead code elimination. + */ +//#define DEBUG 1 + +static int pxa_scan = 1; + +static int i2c_pxa_readbytes(struct i2c_adapter *i2c_adap, char *buf, + int count, int last) +{ + + int i, timeout=0; + struct i2c_algo_pxa_data *adap = i2c_adap->algo_data; + + /* increment number of bytes to read by one -- read dummy byte */ + for (i = 0; i <= count; i++) { + if (i!=0) { + /* set ACK to NAK for last received byte ICR[ACKNAK] = 1 + only if not a repeated start */ + + if ((i == count) && last) { + adap->transfer( last, I2C_RECEIVE, 0); + } else { + adap->transfer( 0, I2C_RECEIVE, 1); + } + + timeout = adap->wait_for_interrupt(I2C_RECEIVE); + +#ifdef DEBUG + if (timeout==BUS_ERROR) { + dev_dbg(&i2c_adap->dev, "read bus error, forcing reset\n"); + adap->reset(); + return I2C_RETRY; + } else +#endif + if (timeout == -ERESTARTSYS) { + adap->abort(); + return timeout; + } else + if (timeout) { + dev_dbg(&i2c_adap->dev, "read timeout, forcing reset\n"); + adap->reset(); + return I2C_RETRY; + } + + } + + if (i) { + buf[i - 1] = adap->read_byte(); + } else { + adap->read_byte(); /* dummy read */ + } + } + return (i - 1); +} + +static int i2c_pxa_sendbytes(struct i2c_adapter *i2c_adap, const char *buf, + int count, int last) +{ + + struct i2c_algo_pxa_data *adap = i2c_adap->algo_data; + int wrcount, timeout; + + for (wrcount=0; wrcountwrite_byte(buf[wrcount]); + if ((wrcount==(count-1)) && last) { + adap->transfer( last, I2C_TRANSMIT, 0); + } else { + adap->transfer( 0, I2C_TRANSMIT, 1); + } + + timeout = adap->wait_for_interrupt(I2C_TRANSMIT); + +#ifdef DEBUG + if (timeout==BUS_ERROR) { + dev_dbg(&i2c_adap->dev, "send bus error, forcing reset\n"); + adap->reset(); + return I2C_RETRY; + } else +#endif + if (timeout == -ERESTARTSYS) { + adap->abort(); + return timeout; + } else + if (timeout) { + dev_dbg(&i2c_adap->dev, "send timeout, forcing reset\n"); + adap->reset(); + return I2C_RETRY; + } + } + return (wrcount); +} + + +static inline int i2c_pxa_set_ctrl_byte(struct i2c_algo_pxa_data * adap, struct i2c_msg *msg) +{ + u16 flags = msg->flags; + u8 addr; + addr = (u8) ( (0x7f & msg->addr) << 1 ); + if (flags & I2C_M_RD ) + addr |= 1; + if (flags & I2C_M_REV_DIR_ADDR ) + addr ^= 1; + adap->write_byte(addr); + return 0; +} + +static int i2c_pxa_do_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) +{ + struct i2c_algo_pxa_data * adap; + struct i2c_msg *pmsg=NULL; + int i; + int ret=0, timeout; + + adap = i2c_adap->algo_data; + + timeout = adap->wait_bus_not_busy(); + + if (timeout) { + return I2C_RETRY; + } + + for (i = 0;ret >= 0 && i < num; i++) { + int last = i + 1 == num; + pmsg = &msgs[i]; + + ret = i2c_pxa_set_ctrl_byte(adap,pmsg); + + /* Send START */ + if (i == 0) { + adap->start(); + } else { + adap->repeat_start(); + } + + adap->transfer(0, I2C_TRANSMIT, 0); + + /* Wait for ITE (transmit empty) */ + timeout = adap->wait_for_interrupt(I2C_TRANSMIT); + +#ifdef DEBUG + /* Check for ACK (bus error) */ + if (timeout==BUS_ERROR) { + dev_dbg(&i2c_adap->dev, "xfer bus error, forcing reset\n"); + adap->reset(); + return I2C_RETRY; + } else +#endif + if (timeout == -ERESTARTSYS) { + adap->abort(); + return timeout; + } else + if (timeout) { + dev_dbg(&i2c_adap->dev, "xfer timeout, forcing reset\n"); + adap->reset(); + return I2C_RETRY; + } +/* FIXME: handle arbitration... */ +#if 0 + /* Check for bus arbitration loss */ + if (adap->arbitration_loss()) { + printk("Arbitration loss detected \n"); + adap->reset(); + return I2C_RETRY; + } +#endif + + /* Read */ + if (pmsg->flags & I2C_M_RD) { + /* read bytes into buffer*/ + ret = i2c_pxa_readbytes(i2c_adap, pmsg->buf, pmsg->len, last); +#if DEBUG > 2 + if (ret != pmsg->len) { + dev_dbg(&i2c_adap->dev, "i2c_pxa_do_xfer read %d/%d bytes\n", + ret, pmsg->len); + } else { + dev_dbg(&i2c_adap->dev, "i2c_pxa_do_xfer: read %d bytes\n",ret); + } +#endif + } else { /* Write */ + ret = i2c_pxa_sendbytes(i2c_adap, pmsg->buf, pmsg->len, last); +#if DEBUG > 2 + if (ret != pmsg->len) { + dev_dbg(&i2c_adap->dev, "i2c_pxa_do_xfer wrote %d/%d bytes\n", + ret, pmsg->len); + } else { + dev_info(&i2c_adap->dev, "i2c_pxa_do_xfer wrote %d bytes\n",ret); + } +#endif + } + } + + if (ret<0) { + return ret; + } else { + return i; + } +} + +static int i2c_pxa_valid_messages( struct device *dev, struct i2c_msg msgs[], int num) +{ + int i; + if (num < 1 || num > MAX_MESSAGES) { + dev_dbg(dev, "%d messages of max %d\n", num, MAX_MESSAGES); + return -EINVAL; + } + + /* check consistency of our messages */ + for (i=0; idev, msgs, num); + if (retval > 0) + { + int i; + for (i=i2c_adap->retries; i>=0; i--) { + int retval = i2c_pxa_do_xfer(i2c_adap,msgs,num); + if (retval != I2C_RETRY) { + return retval; + } + dev_dbg(&i2c_adap->dev, "retrying transmission\n"); + udelay(100); + } + dev_dbg(&i2c_adap->dev, "retried %i times\n", i2c_adap->retries); + return -EREMOTEIO; + + } + return retval; +} + +static u32 i2c_pxa_functionality(struct i2c_adapter * adapter) +{ + /* Emulate the SMBUS functions */ + return I2C_FUNC_SMBUS_EMUL; +} + +struct i2c_algorithm i2c_pxa_algorithm = { + .name = "PXA I2C Algorithm", + .id = I2C_ALGO_PXA, + .master_xfer = i2c_pxa_xfer, + .functionality = i2c_pxa_functionality, +}; + +/* + * registering functions to load algorithms at runtime + */ +int i2c_pxa_add_bus(struct i2c_adapter *i2c_adap) +{ + struct i2c_algo_pxa_data *adap = i2c_adap->algo_data; + + i2c_adap->algo = &i2c_pxa_algorithm; + + /* register new adapter to i2c module... */ + i2c_add_adapter(i2c_adap); + + adap->reset(); + + /* scan bus */ + if (pxa_scan) { + int i; + for (i = 0x02; i < 0xff; i+=2) { + if (i==(I2C_PXA_SLAVE_ADDR<<1)) continue; + + if (adap->wait_bus_not_busy()) { + dev_err(&i2c_adap->dev, "TIMEOUT while scanning bus\n"); + return -EIO; + } + adap->write_byte(i); + adap->start(); + adap->transfer(0, I2C_TRANSMIT, 0); + + if ((adap->wait_for_interrupt(I2C_TRANSMIT) != BUS_ERROR)) { + dev_info(&i2c_adap->dev, "found device 0x%02x\n", i>>1); + adap->abort(); + } else { + adap->stop(); + } + udelay(adap->udelay); + } + } + return 0; +} + +int i2c_pxa_del_bus(struct i2c_adapter *i2c_adap) +{ + return i2c_del_adapter(i2c_adap); +} + +EXPORT_SYMBOL(i2c_pxa_add_bus); +EXPORT_SYMBOL(i2c_pxa_del_bus); + +MODULE_PARM(pxa_scan, "i"); +MODULE_PARM_DESC(pxa_scan, "Scan for active chips on the bus"); + +MODULE_AUTHOR("Intrinsyc Software Inc."); +MODULE_LICENSE("GPL"); diff -x .svn -urN linux-2.6.8-rc2/drivers/i2c/algos/Makefile linux-2.6.8-rc2-pnp1/drivers/i2c/algos/Makefile --- linux-2.6.8-rc2/drivers/i2c/algos/Makefile 2004-06-16 07:19:43.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/i2c/algos/Makefile 2004-07-27 14:02:47.000000000 +0200 @@ -5,6 +5,7 @@ obj-$(CONFIG_I2C_ALGOBIT) += i2c-algo-bit.o obj-$(CONFIG_I2C_ALGOPCF) += i2c-algo-pcf.o obj-$(CONFIG_I2C_ALGOITE) += i2c-algo-ite.o +obj-$(CONFIG_I2C_PXA) += i2c-algo-pxa.o ifeq ($(CONFIG_I2C_DEBUG_ALGO),y) EXTRA_CFLAGS += -DDEBUG diff -x .svn -urN linux-2.6.8-rc2/drivers/i2c/busses/i2c-pxa.c linux-2.6.8-rc2-pnp1/drivers/i2c/busses/i2c-pxa.c --- linux-2.6.8-rc2/drivers/i2c/busses/i2c-pxa.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/i2c/busses/i2c-pxa.c 2004-07-27 14:02:47.000000000 +0200 @@ -0,0 +1,367 @@ +/* + * i2c_pxa.c + * + * I2C adapter for the PXA I2C bus access + * + * Copyright (C) 2002 Intrinsyc Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History: + * Apr 2002: Initial version [CS] + * Jun 2002: Properly seperated algo/adap [FB] + * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] + * Jan 2003: added limited signal handling [Kai-Uwe Bloem] + * Jun 2003: updated for 2.5 [Dustin McIntire] + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include /* for IRQ_I2C */ +#include + +/* + * Set this to zero to remove all debug statements via dead code elimination. + */ +//#define DEBUG 1 + +#if DEBUG +static unsigned int i2c_debug = DEBUG; +#else +#define i2c_debug 0 +#endif + +static int irq = 0; +static volatile int i2c_pending = 0; /* interrupt pending when 1 */ +static volatile int bus_error = 0; +static volatile int tx_finished = 0; +static volatile int rx_finished = 0; + +static wait_queue_head_t i2c_wait; +static void i2c_pxa_transfer( int lastbyte, int receive, int midbyte); + +static spinlock_t i2c_pxa_irqlock = SPIN_LOCK_UNLOCKED; + +/* place a byte in the transmit register */ +static void i2c_pxa_write_byte(u8 value) +{ + IDBR = value; +} + +/* read byte in the receive register */ +static u8 i2c_pxa_read_byte(void) +{ + return (u8) (0xff & IDBR); +} + +static void i2c_pxa_start(void) +{ + unsigned long icr = ICR; + icr |= ICR_START; + icr &= ~(ICR_STOP | ICR_ALDIE | ICR_ACKNAK); + ICR = icr; + + bus_error=0; /* clear any bus_error from previous txfers */ + tx_finished=0; /* clear rx and tx interrupts from previous txfers */ + rx_finished=0; + i2c_pending = 0; +} + +static void i2c_pxa_repeat_start(void) +{ + unsigned long icr = ICR; + icr |= ICR_START; + icr &= ~(ICR_STOP | ICR_ALDIE); + ICR = icr; + + bus_error=0; /* clear any bus_error from previous txfers */ + tx_finished=0; /* clear rx and tx interrupts from previous txfers */ + rx_finished=0; + i2c_pending = 0; +} + +static void i2c_pxa_stop(void) +{ + unsigned long icr = ICR; + icr |= ICR_STOP; + icr &= ~(ICR_START); + ICR = icr; +} + +static void i2c_pxa_midbyte(void) +{ + unsigned long icr = ICR; + icr &= ~(ICR_START | ICR_STOP); + ICR = icr; +} + +static void i2c_pxa_abort(void) +{ + unsigned long timeout = jiffies + HZ/4; + +#ifdef PXA_ABORT_MA + while ((long)(timeout - jiffies) > 0 && (ICR & ICR_TB)) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } + + ICR |= ICR_MA; + udelay(100); +#else + while ((long)(timeout - jiffies) > 0 && (IBMR & 0x1) == 0) { + i2c_pxa_transfer( 1, I2C_RECEIVE, 1); + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } +#endif + ICR &= ~(ICR_MA | ICR_START | ICR_STOP); +} + +static int i2c_pxa_wait_bus_not_busy(void) +{ + int timeout = DEF_TIMEOUT; + + while (timeout-- && (ISR & ISR_IBB)) { + udelay(100); /* wait for 100 us */ + } + + return (timeout<=0); +} + +static void i2c_pxa_wait_for_ite(void) +{ + unsigned long flags; + if (irq > 0) { + spin_lock_irqsave(&i2c_pxa_irqlock, flags); + if (i2c_pending == 0) { + interruptible_sleep_on_timeout(&i2c_wait, I2C_SLEEP_TIMEOUT ); + } + i2c_pending = 0; + spin_unlock_irqrestore(&i2c_pxa_irqlock, flags); + } else { + udelay(100); + } +} + +static int i2c_pxa_wait_for_int(int wait_type) +{ + int timeout = DEF_TIMEOUT; +#ifdef DEBUG + if (bus_error) + printk(KERN_INFO"i2c_pxa_wait_for_int: Bus error on enter\n"); + if (rx_finished) + printk(KERN_INFO"i2c_pxa_wait_for_int: Receive interrupt on enter\n"); + if (tx_finished) + printk(KERN_INFO"i2c_pxa_wait_for_int: Transmit interrupt on enter\n"); +#endif + + if (wait_type == I2C_RECEIVE) { /* wait on receive */ + + do { + i2c_pxa_wait_for_ite(); + } while (!(rx_finished) && timeout-- && !signal_pending(current)); + +#ifdef DEBUG + if (timeout<0) { + if (tx_finished) + printk("I2C: received a tx interrupt while waiting on a rx in wait_for_int"); + } +#endif + } else { /* wait on transmit */ + + do { + i2c_pxa_wait_for_ite(); + } while (!(tx_finished) && timeout-- && !signal_pending(current)); + +#ifdef DEBUG + if (timeout<0) { + if (rx_finished) + printk("i2c: received a rx interrupt while waiting on a tx in wait_for_int"); + } +#endif + } + + udelay(ACK_DELAY); /* this is needed for the bus error */ + + tx_finished=0; + rx_finished=0; + + if (bus_error) { + bus_error=0; + if (i2c_debug > 2)printk("wait_for_int: error - no ack\n"); + return BUS_ERROR; + } + + if (signal_pending(current)) { + return (-ERESTARTSYS); + } else + if (timeout < 0) { + if (i2c_debug > 2)printk("wait_for_int: timeout\n"); + return(-EIO); + } else + return(0); +} + +static void i2c_pxa_transfer(int lastbyte, int receive, int midbyte) +{ + if (lastbyte) { + if (receive==I2C_RECEIVE) ICR |= ICR_ACKNAK; + i2c_pxa_stop(); + } else + if (midbyte) { + i2c_pxa_midbyte(); + } + ICR |= ICR_TB; +} + +static void i2c_pxa_reset( void) +{ +#ifdef DEBUG + printk("Resetting I2C Controller Unit\n"); +#endif + + /* abort any transfer currently under way */ + i2c_pxa_abort(); + + /* reset according to 9.8 */ + ICR = ICR_UR; + ISR = I2C_ISR_INIT; + ICR &= ~ICR_UR; + + /* set the global I2C clock on */ + CKEN |= CKEN14_I2C; + + /* set our slave address */ + ISAR = I2C_PXA_SLAVE_ADDR; + + /* set control register values */ + ICR = I2C_ICR_INIT; + + /* clear any leftover states from prior transmissions */ + i2c_pending = rx_finished = tx_finished = bus_error = 0; + + /* enable unit */ + ICR |= ICR_IUE; + udelay(100); +} + +static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id, struct pt_regs *regs) +{ + unsigned long flags; + int status, wakeup = 0; + status = (ISR); + + if (status & ISR_BED) { + (ISR) |= ISR_BED; + bus_error=ISR_BED; + wakeup = 1; + } + if (status & ISR_ITE) { + (ISR) |= ISR_ITE; + tx_finished=ISR_ITE; + wakeup = 1; + } + if (status & ISR_IRF) { + (ISR) |= ISR_IRF; + rx_finished=ISR_IRF; + wakeup = 1; + } + if (wakeup) { + spin_lock_irqsave(&i2c_pxa_irqlock, flags); + i2c_pending = 1; + spin_unlock_irqrestore(&i2c_pxa_irqlock, flags); + wake_up_interruptible(&i2c_wait); + } + return IRQ_HANDLED; +} + +static int i2c_pxa_resource_init(void) +{ + init_waitqueue_head(&i2c_wait); + + if (request_irq(IRQ_I2C, &i2c_pxa_handler, 0, "I2C", 0) < 0) { + irq = 0; + if (i2c_debug) + printk(KERN_INFO "I2C: Failed to register I2C irq %i\n", IRQ_I2C); + return -ENODEV; + } + return 0; +} + +static void i2c_pxa_resource_release( void) +{ + if (irq > 0) { + free_irq(irq,0); + irq=0; + } +} + +static struct i2c_algo_pxa_data i2c_pxa_data = { + write_byte: i2c_pxa_write_byte, + read_byte: i2c_pxa_read_byte, + + start: i2c_pxa_start, + repeat_start: i2c_pxa_repeat_start, + stop: i2c_pxa_stop, + abort: i2c_pxa_abort, + + wait_bus_not_busy: i2c_pxa_wait_bus_not_busy, + wait_for_interrupt: i2c_pxa_wait_for_int, + transfer: i2c_pxa_transfer, + reset: i2c_pxa_reset, + + udelay: 10, + timeout: DEF_TIMEOUT, +}; + +static struct i2c_adapter i2c_pxa_ops = { + .owner = THIS_MODULE, + .id = I2C_ALGO_PXA, + .name = "PXA i2c adapter", + .algo_data = &i2c_pxa_data, + .retries = 2, +}; + +extern int i2c_pxa_add_bus(struct i2c_adapter *); +extern int i2c_pxa_del_bus(struct i2c_adapter *); + +static int __init i2c_adap_pxa_init(void) +{ + if (i2c_pxa_resource_init() == 0) { + if (i2c_pxa_add_bus(&i2c_pxa_ops) < 0) { + i2c_pxa_resource_release(); + printk(KERN_INFO "I2C: Failed to add bus\n"); + return -ENODEV; + } + } else { + return -ENODEV; + } + + return 0; +} + +static void i2c_adap_pxa_exit(void) +{ + i2c_pxa_del_bus(&i2c_pxa_ops); + i2c_pxa_resource_release(); +} + +MODULE_DESCRIPTION("PXA2x0 i2c driver"); +MODULE_LICENSE("GPL"); + +module_init(i2c_adap_pxa_init); +module_exit(i2c_adap_pxa_exit); diff -x .svn -urN linux-2.6.8-rc2/drivers/i2c/busses/Kconfig linux-2.6.8-rc2-pnp1/drivers/i2c/busses/Kconfig --- linux-2.6.8-rc2/drivers/i2c/busses/Kconfig 2004-06-16 07:19:52.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/i2c/busses/Kconfig 2004-07-27 14:02:46.000000000 +0200 @@ -396,4 +396,15 @@ This driver can also be built as a module. If so, the module will be called i2c-voodoo3. +config I2C_PXA + tristate "I2C interface in Intel PXA2x0" + depends on ARCH_PXA && I2C + help + This supports the use of the PXA I2C interface found on the Intel + PXA 25x and PXA 26x systems. Say Y if you have one of these. + You should also say Y for the PXA I2C peripheral driver support below. + + To compile this driver as a module, say M here: the + modules will be called i2c-pxa and i2c-algo-pxa. + endmenu diff -x .svn -urN linux-2.6.8-rc2/drivers/i2c/busses/Makefile linux-2.6.8-rc2-pnp1/drivers/i2c/busses/Makefile --- linux-2.6.8-rc2/drivers/i2c/busses/Makefile 2004-06-16 07:18:57.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/i2c/busses/Makefile 2004-07-27 14:02:46.000000000 +0200 @@ -22,6 +22,7 @@ obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o obj-$(CONFIG_I2C_PROSAVAGE) += i2c-prosavage.o +obj-$(CONFIG_I2C_PXA) += i2c-pxa.o obj-$(CONFIG_I2C_RPXLITE) += i2c-rpx.o obj-$(CONFIG_I2C_SAVAGE4) += i2c-savage4.o obj-$(CONFIG_I2C_SIS5595) += i2c-sis5595.o @@ -30,6 +31,7 @@ obj-$(CONFIG_I2C_VIA) += i2c-via.o obj-$(CONFIG_I2C_VIAPRO) += i2c-viapro.o obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o +obj-$(CONFIG_I2C_PXA) += i2c-pxa.o obj-$(CONFIG_SCx200_ACB) += scx200_acb.o obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o diff -x .svn -urN linux-2.6.8-rc2/drivers/ide/diff linux-2.6.8-rc2-pnp1/drivers/ide/diff --- linux-2.6.8-rc2/drivers/ide/diff 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/ide/diff 2004-07-27 14:02:05.000000000 +0200 @@ -0,0 +1,32 @@ +--- /ptx/kernel/linux-2.4.19-rmk7-pxa2-ssv1-ide/drivers/ide/ide.c 2003-10-01 09:31:51.000000000 +0200 ++++ ide-weihua.c 2004-07-13 13:16:28.429882240 +0200 +@@ -158,6 +161,7 @@ + #include + + #include "ide_modes.h" ++#include "pnpX110-ipe-pii.h" + + #ifdef CONFIG_KMOD + #include +@@ -326,7 +330,11 @@ + + /* Add default hw interfaces */ + ide_old_init_default_hwifs(); ++#if defined(CONFIG_SA1100_PNP1110) || defined(CONFIG_ARCH_PXA_PNP2110) ++ ide_init_default_pnpx110_hwifs(); ++#else + ide_init_default_hwifs(); ++#endif + + #ifdef CONFIG_BLK_DEV_HD + /* Check for any clashes with hd.c driver */ +@@ -3697,6 +3705,9 @@ + pnpide_init(1); + } + #endif /* CONFIG_BLK_DEV_ISAPNP */ ++#if defined(CONFIG_SA1100_PNP1110) || defined(CONFIG_ARCH_PXA_PNP2110) ++ pnpx110_ide_init(); ++#endif + } + + void __init ide_init_builtin_drivers (void) diff -x .svn -urN linux-2.6.8-rc2/drivers/ide/ide.c linux-2.6.8-rc2-pnp1/drivers/ide/ide.c --- linux-2.6.8-rc2/drivers/ide/ide.c 2004-07-27 14:08:04.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/ide/ide.c 2004-07-27 14:02:04.000000000 +0200 @@ -2070,6 +2070,12 @@ buddha_init(); } #endif /* CONFIG_BLK_DEV_BUDDHA */ +#ifdef CONFIG_BLK_DEV_FZKIDE + { + extern void fzkide_init(void); + fzkide_init(); + } +#endif /* BLK_DEV_FZKIDE */ #ifdef CONFIG_BLK_DEV_IDEPNP pnpide_init(); #endif diff -x .svn -urN linux-2.6.8-rc2/drivers/ide/ide-fzk.c linux-2.6.8-rc2-pnp1/drivers/ide/ide-fzk.c --- linux-2.6.8-rc2/drivers/ide/ide-fzk.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/ide/ide-fzk.c 2004-07-27 14:02:05.000000000 +0200 @@ -0,0 +1,280 @@ +/* + * linux/drivers/ide/legacy/fzkide.c Version 0.1 Jan 19, 2004 + * + * Copyright (C) 2004 Weihua Zhang, FZK + * Copyright (C) 2004 Robert Schwebel, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Jan 19, 2004 support only pio mode + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#if !defined(CONFIG_ARCH_PXA_PNP2110) +#error "Nobody has tested this on a non-PNP2110 board yet..." +#endif + +#include +#include + +#define DRIVER_NAME "fzkide" + +/* + * The followings are originally defined in drivers/pcmcia/pxa/pxa.h + * FIXME: check for conflicts + */ +#define MCXX_SETUP_MASK (0x7f) +#define MCXX_ASST_MASK (0x1f) +#define MCXX_HOLD_MASK (0x3f) +#define MCXX_SETUP_SHIFT (0) +#define MCXX_ASST_SHIFT (7) +#define MCXX_HOLD_SHIFT (14) + +extern int platform_add_devices(struct platform_device **devs, int num); + +/* + * The following table is according to the ATA/ATAIP-6 T13 1410D Revision 3b. + * It is noted that there is a pio mode 5, but the timing is not included + * in the Revision 3b. + * setup asst hold (ns) + */ +unsigned short fzkide_pio_timing[5][3] = {{70, 165, 20}, /* pio mode 0 */ + {50, 125, 15}, /* pio mode 1 */ + {30, 100, 10}, /* pio mode 2 */ + {30, 80, 10}, /* pio mode 3 */ + {25, 70, 10} /* pio mode 4 */ +}; + +static inline u_int pxa_mcxx_hold(u_int pcmcia_cycle_ns, u_int mem_clk_10khz) +{ + u_int code = pcmcia_cycle_ns * mem_clk_10khz; + return (code / 300000) + ((code % 300000) ? 1 : 0); +} + +static inline u_int pxa_mcxx_asst(u_int pcmcia_cycle_ns, u_int mem_clk_10khz) +{ + u_int code = pcmcia_cycle_ns * mem_clk_10khz; + return (code / 300000) + ((code % 300000) ? 1 : 0); +} + +static inline u_int pxa_mcxx_setup(u_int pcmcia_cycle_ns, u_int mem_clk_10khz) +{ + u_int code = pcmcia_cycle_ns * mem_clk_10khz; + return (code / 100000) + ((code % 100000) ? 1 : 0) + 1; +} + +static void fzkide_tune_drive(ide_drive_t *drive, u8 pio_mode_wanted) +{ + u8 pio_mode = ide_get_best_pio_mode(drive, 255, 5, NULL); + unsigned int clock = get_memclk_frequency_10khz(); + + if (pio_mode > 4) + pio_mode = 4; + + printk("using pio mode %d\n", pio_mode); + + /* + * set PCMCIA I/O timing for this best pio mode + * FIXME: make this use only "legal" ressources... + */ + MCIO1 = ((pxa_mcxx_setup(fzkide_pio_timing[pio_mode][0], clock) & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) + | ((pxa_mcxx_asst (fzkide_pio_timing[pio_mode][1], clock) & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) + | ((pxa_mcxx_hold (fzkide_pio_timing[pio_mode][2], clock) & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); + + return; +} + +static int fzkide_probe(struct device *dev) +{ + hw_regs_t hw; + ide_hwif_t *hwif; + int i; + unsigned long reg; + int ret = -ENODEV; + struct resource *res = NULL; + unsigned long physaddr, ioaddr; + size_t iosize; + struct platform_device *pdev = to_platform_device(dev); + + /* probe if this is our device */ + printk(KERN_INFO "trying to probe fzkide IDE port\n"); + if (!pdev || strncmp (pdev->name, "fzkide", 6)) return ret; + + /* allocate & register memory */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk("%s: no mem resource defined.\n", DRIVER_NAME); + goto out; + } + + physaddr = res->start; + iosize = res->end - res->start; + + if (!request_mem_region(physaddr, iosize, DRIVER_NAME)) { + printk("%s: device busy.\n", DRIVER_NAME); + ret = -EBUSY; + goto out; + } + + ioaddr = (u32)ioremap(physaddr, iosize); + if (!ioaddr) { + printk("%s: ioremap failed.\n", DRIVER_NAME); + ret = -ENOMEM; + goto rel_mem; + } + + memset(&hw, 0, sizeof(hw)); + + reg = ioaddr + 0x0000; /* data port */ + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw.io_ports[i] = reg; + reg += 2; /* Weihua doesn't use A0 for IDE */ + } + + hw.io_ports[IDE_CONTROL_OFFSET] = + ioaddr + 0x100C; /* control port */ + + hw.dma = NO_DMA; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res->start) { + printk("%s: IRQ not defined.\n", DRIVER_NAME); + ret = -EIO; + goto rel_mem; + } + + hw.irq = res->start; + + if (res->flags & IORESOURCE_IRQ_HIGHEDGE) + set_irq_type(hw.irq, IRQT_RISING); + if (res->flags & IORESOURCE_IRQ_LOWEDGE) + set_irq_type(hw.irq, IRQT_FALLING); + + hwif->tuneproc = &fzkide_tune_drive; + hwif->drives[0].autotune = 1; + hwif->drives[1].autotune = 1; + + /* register IDE device */ + i = ide_register_hw(&hw, &hwif); + + if (i == -1) { + printk(KERN_WARNING "%s: registering IDE failed\n", DRIVER_NAME); + ret = -EIO; + goto rel_mem; + } + + dev_set_drvdata(dev, hwif); + ret = 0; + goto out; + +rel_mem: + release_mem_region(physaddr, iosize); +out: + return ret; +} + +static int fzkide_remove(struct device *dev) +{ + struct resource *res = NULL; + ide_hwif_t *hwif = dev_get_drvdata(dev); + struct platform_device *pdev = to_platform_device(dev); + unsigned long physaddr; + size_t iosize; + + if (!hwif) { + printk(KERN_ERR "%s: Unable to remove device, please report.\n", DRIVER_NAME); + return -EIO; + } + + ide_unregister(hwif->index); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk("%s: no mem resource defined.\n", DRIVER_NAME); + return -EIO; + } + + physaddr = res->start; + iosize = res->end - res->start; + + release_mem_region(physaddr, iosize); + + return 0; +} + +/* driver model */ + +static struct device_driver fzkide_driver = { + .name = "fzkide", + .bus = &platform_bus_type, + .probe = fzkide_probe, + .remove = fzkide_remove, +}; + +/* device and ressources */ + +static struct resource fzkide_resources[] = { + { + .start = _PCMCIA(1), + .end = _PCMCIA(1) + PCMCIAIOSp, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, + }, + { + .start = IRQ_GPIO(1), + .end = IRQ_GPIO(1), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + }, +}; + +static struct platform_device fzkide_device = { + .name = "fzkide", + .id = 0, + .num_resources = ARRAY_SIZE(fzkide_resources), + .resource = fzkide_resources, +}; + +static struct platform_device *devices[] __initdata = { + &fzkide_device, +}; + +void __init fzkide_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); + driver_register(&fzkide_driver); +} + diff -x .svn -urN linux-2.6.8-rc2/drivers/ide/Kconfig linux-2.6.8-rc2-pnp1/drivers/ide/Kconfig --- linux-2.6.8-rc2/drivers/ide/Kconfig 2004-07-27 14:08:04.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/ide/Kconfig 2004-07-27 14:02:04.000000000 +0200 @@ -964,6 +964,14 @@ People with SCSI-only systems can say N here. +config BLK_DEV_FZKIDE + bool "FZK IDE Port" + depends on ARCH_PXA && IDE_GENERIC + help + Support for the FZK IDE port on some PNP2110 base boards. This is a + CPLD based port which makes a real IDE port out of a PXA2xx PCMCIA + port. + if IDE_CHIPSETS comment "Note: most of these also require special kernel boot parameters" diff -x .svn -urN linux-2.6.8-rc2/drivers/ide/Makefile linux-2.6.8-rc2-pnp1/drivers/ide/Makefile --- linux-2.6.8-rc2/drivers/ide/Makefile 2004-07-27 14:08:04.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/ide/Makefile 2004-07-27 14:02:06.000000000 +0200 @@ -24,6 +24,7 @@ ide-core-$(CONFIG_BLK_DEV_IDE_TCQ) += ide-tcq.o ide-core-$(CONFIG_PROC_FS) += ide-proc.o ide-core-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o +ide-core-$(CONFIG_BLK_DEV_FZKIDE) += ide-fzk.o # built-in only drivers from arm/ ide-core-$(CONFIG_IDE_ARM) += arm/ide_arm.o diff -x .svn -urN linux-2.6.8-rc2/drivers/input/Kconfig linux-2.6.8-rc2-pnp1/drivers/input/Kconfig --- linux-2.6.8-rc2/drivers/input/Kconfig 2004-06-16 07:18:58.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/input/Kconfig 2004-07-27 14:00:37.000000000 +0200 @@ -25,7 +25,7 @@ comment "Userland interfaces" config INPUT_MOUSEDEV - tristate "Mouse interface" if EMBEDDED + tristate "Mouse interface" default y depends on INPUT ---help--- diff -x .svn -urN linux-2.6.8-rc2/drivers/Makefile linux-2.6.8-rc2-pnp1/drivers/Makefile --- linux-2.6.8-rc2/drivers/Makefile 2004-07-27 14:08:04.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/Makefile 2004-07-27 14:01:03.000000000 +0200 @@ -51,3 +51,4 @@ obj-$(CONFIG_EISA) += eisa/ obj-$(CONFIG_CPU_FREQ) += cpufreq/ obj-y += firmware/ +obj-$(CONFIG_FPBUS) += fpbus/ diff -x .svn -urN linux-2.6.8-rc2/drivers/mtd/maps/innokom.c linux-2.6.8-rc2-pnp1/drivers/mtd/maps/innokom.c --- linux-2.6.8-rc2/drivers/mtd/maps/innokom.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/mtd/maps/innokom.c 2004-07-27 14:00:24.000000000 +0200 @@ -0,0 +1,228 @@ +/* + * Map driver for the Auerswald Innokom platform. + * + * Authors: Kai-Uwe Bloem, Robert Schwebel, Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * (C) 2003 Pengutronix + * (C) 2003 Auerswald GmbH & Co. KG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define WINDOW_ADDR 0 +#define WINDOW_SIZE (128*1024*1024) /* 2 Flashes in PXA nCS banks #0, #1 */ + +static __u8 innokom_read8(struct map_info *map, unsigned long ofs) +{ + return *(__u8 *)(map->map_priv_1 + ofs); +} + +static __u16 innokom_read16(struct map_info *map, unsigned long ofs) +{ + return *(__u16 *)(map->map_priv_1 + ofs); +} + +static __u32 innokom_read32(struct map_info *map, unsigned long ofs) +{ + return *(__u32 *)(map->map_priv_1 + ofs); +} + +static void innokom_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) +{ + memcpy(to, (void *)(map->map_priv_1 + from), len); +} + +static void innokom_write8(struct map_info *map, __u8 d, unsigned long adr) +{ + *(__u8 *)(map->map_priv_1 + adr) = d; +} + +static void innokom_write16(struct map_info *map, __u16 d, unsigned long adr) +{ + *(__u16 *)(map->map_priv_1 + adr) = d; +} + +static void innokom_write32(struct map_info *map, __u32 d, unsigned long adr) +{ + *(__u32 *)(map->map_priv_1 + adr) = d; +} + +static void innokom_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) +{ + memcpy((void *)(map->map_priv_1 + to), from, len); +} + +static struct map_info innokom_map = { + name: "Innokom flash", + size: WINDOW_SIZE, + read8: innokom_read8, + read16: innokom_read16, + read32: innokom_read32, + copy_from: innokom_copy_from, + write8: innokom_write8, + write16: innokom_write16, + write32: innokom_write32, + copy_to: innokom_copy_to +}; + + +static struct mtd_partition innokom_partitions_16M[] = { + { + name: "U-Boot", + size: 0x00040000, /* 256 kB */ + offset: 0x00000000, + /* mask_flags: MTD_WRITEABLE force read-only */ + },{ + name: "Firmware-1", + size: 0x000C0000, /* 768 kB */ + offset: 0x00040000, + },{ + name: "Firmware-2", + size: 0x00800000, /* 8 MB */ + offset: 0x00100000, + },{ + name: "Data", + size: 0x00700000, /* 7 MB */ + offset: 0x00900000 + } +}; + +#if 0 +static struct mtd_partition innokom_partitions_32M[] = { + { + name: "U-Boot", + size: 0x00040000, /* 256 kB */ + offset: 0x00000000, + /* mask_flags: MTD_WRITEABLE force read-only */ + },{ + name: "Firmware-1", + size: 0x007E0000, /* 8 MB - 128 kB */ + offset: 0x00040000, + },{ + name: "Firmware-2", + size: 0x007E0000, /* 8 MB - 128 kB */ + offset: 0x00820000, + },{ + name: "Data", + size: 0x01000000, /* 16 MB */ + offset: 0x01000000 + } +}; +#endif + +static struct mtd_partition innokom_partitions_64M[] = { + { + name: "U-Boot", + size: 0x00040000, /* 256 kB */ + offset: 0x00000000, + /* mask_flags: MTD_WRITEABLE force read-only */ + },{ + name: "Firmware-1", + size: 0x00FE0000, /* 16 MB - 128 kB */ + offset: 0x00040000, + },{ + name: "Firmware-2", + size: 0x00FE0000, /* 16 MB - 128 kB */ + offset: 0x01020000, + },{ + name: "Data", + size: 0x02000000, /* 32 MB */ + offset: 0x02000000 + } +}; + +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) + +static struct mtd_info *mymtd; +static struct mtd_partition *parsed_parts; + +static int __init init_innokom(void) +{ + struct mtd_partition *parts; + int nb_parts = 0; + int parsed_nr_parts = 0; + char *part_type = "static"; + + innokom_map.buswidth = (BOOT_DEF & 1) ? 2 : 4; + printk( "Probing Auerswald Innokom flash at physical address 0x%08x (%d-bit buswidth)\n", + WINDOW_ADDR, innokom_map.buswidth * 8 ); + /* FIXME: RS: is the "align" parameter (last one) correct? I + * could not find an example for it... */ + innokom_map.map_priv_1 = (unsigned long)__ioremap(WINDOW_ADDR, WINDOW_SIZE, 0, 0); + if (!innokom_map.map_priv_1) { + printk("Failed to ioremap\n"); + return -EIO; + } + mymtd = do_map_probe("cfi_probe", &innokom_map); + if (!mymtd) { + iounmap((void *)innokom_map.map_priv_1); + return -ENXIO; + } + mymtd->owner = THIS_MODULE; + + if (parsed_nr_parts > 0) { + parts = parsed_parts; + + } else switch (mymtd->size) { + case 64*1024*1024: + parts = innokom_partitions_64M; + part_type = "static (64M)"; + nb_parts = NB_OF(innokom_partitions_64M); + break; + case 32*1024*1024: +#if 0 + parts = innokom_partitions_32M; + part_type = "static (32M)"; + nb_parts = NB_OF(innokom_partitions_32M); + break; +#endif + case 16*1024*1024: + parts = innokom_partitions_16M; + part_type = "static (16M)"; + nb_parts = NB_OF(innokom_partitions_16M); + break; + default: + printk(KERN_WARNING "Can't derive partitioning from MTD size, using 16M as default\n"); + parts = innokom_partitions_16M; + part_type = "static (default)"; + nb_parts = NB_OF(innokom_partitions_16M); + break; + } + if (nb_parts) { + printk(KERN_NOTICE "Using %s partition definition\n", part_type); + add_mtd_partitions(mymtd, parts, nb_parts); + } else { + add_mtd_device(mymtd); + } + return 0; +} + +static void __exit cleanup_innokom(void) +{ + if (mymtd) { + del_mtd_partitions(mymtd); + map_destroy(mymtd); + if (parsed_parts) + kfree(parsed_parts); + } + if (innokom_map.map_priv_1) + iounmap((void *)innokom_map.map_priv_1); + return; +} + +module_init(init_innokom); +module_exit(cleanup_innokom); + diff -x .svn -urN linux-2.6.8-rc2/drivers/mtd/maps/Kconfig linux-2.6.8-rc2-pnp1/drivers/mtd/maps/Kconfig --- linux-2.6.8-rc2/drivers/mtd/maps/Kconfig 2004-07-27 14:08:05.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/mtd/maps/Kconfig 2004-07-27 14:00:24.000000000 +0200 @@ -113,6 +113,20 @@ This provides a driver for the on-board flash of the Intel 'Lubbock' XScale evaluation board. +config MTD_INNOKOM + tristate "CFI Flash device mapped on Auerswald Innokom" + depends on ARCH_INNOKOM && MTD_PARTITIONS && MTD_COMPLEX_MAPPINGS + help + This provides a driver for the on-board flash of the + Auerswald Innokom board. + +config MTD_PNP2110 + tristate "CFI Flash device mapped on PNP/2110" + depends on ARCH_PXA_PNP2110 && MTD_PARTITIONS && MTD_COMPLEX_MAPPINGS + help + This provides a driver for the on-board flash of the SSV PNP2110 + module. For more details about the board see http://www.dnp.com. + config MTD_OCTAGON tristate "JEDEC Flash device mapped on Octagon 5066 SBC" depends on X86 && MTD_JEDEC && MTD_COMPLEX_MAPPINGS diff -x .svn -urN linux-2.6.8-rc2/drivers/mtd/maps/Makefile linux-2.6.8-rc2-pnp1/drivers/mtd/maps/Makefile --- linux-2.6.8-rc2/drivers/mtd/maps/Makefile 2004-07-27 14:08:05.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/mtd/maps/Makefile 2004-07-27 14:00:24.000000000 +0200 @@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o obj-$(CONFIG_MTD_ELAN_104NC) += elan-104nc.o obj-$(CONFIG_MTD_EPXA10DB) += epxa10db-flash.o +obj-$(CONFIG_MTD_INNOKOM) += innokom.o obj-$(CONFIG_MTD_IQ80310) += iq80310.o obj-$(CONFIG_MTD_L440GX) += l440gx.o obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o @@ -64,3 +65,4 @@ obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o obj-$(CONFIG_MTD_DMV182) += dmv182.o +obj-$(CONFIG_MTD_PNP2110) += pnp2110.o diff -x .svn -urN linux-2.6.8-rc2/drivers/mtd/maps/pnp2110.c linux-2.6.8-rc2-pnp1/drivers/mtd/maps/pnp2110.c --- linux-2.6.8-rc2/drivers/mtd/maps/pnp2110.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/mtd/maps/pnp2110.c 2004-07-27 14:00:24.000000000 +0200 @@ -0,0 +1,152 @@ +/* + * Map driver for the SSV PNP/2110-3V platform. + * + * Author: Marco Hasewinkel + * Copyright: (C) 2003 SSV Embedded Systems + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + + +/* This window is probed for flash devices */ +#define WINDOW_ADDR 0x00000000 +#define WINDOW_SIZE (32*1024*1024) + +#define PNP2110_VPP_GPIO 16 + +static void +pnp2110_set_vpp(struct map_info *map, int on) +{ + /* GPIO16: 1=Vpp on 0=Vpp off */ + if (on) + GPSR(PNP2110_VPP_GPIO) |= GPIO_bit(PNP2110_VPP_GPIO); + else + GPCR(PNP2110_VPP_GPIO) |= GPIO_bit(PNP2110_VPP_GPIO); +} + +static struct map_info pnp2110_map = { + .name = "PNP/2110-3V flash", + .size = WINDOW_SIZE, + .phys = WINDOW_ADDR, + .set_vpp = pnp2110_set_vpp, +}; + +static struct mtd_partition pnp2110_partitions[] = { + { + name: "Bootloader", + size: 0x00020000, + offset: 0, + mask_flags: MTD_WRITEABLE /* force read-only */ + },{ + name: "Bootloader env", + size: 0x00020000, + offset: 0x00020000, + mask_flags: MTD_WRITEABLE /* force read-only */ + },{ + name: "Filesystem space", + size: 0x00FC0000, + offset: 0x00040000 + } +}; + +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) + +static struct mtd_info *mymtd; +static struct mtd_partition *parsed_parts; + +static int __init init_pnp2110(void) +{ + struct mtd_partition *parts; + int nb_parts = 0; + int parsed_nr_parts = 0; + char *part_type = "static"; + + pnp2110_map.bankwidth = (BOOT_DEF & 1) ? 2 : 4; + + /* Map flash chips */ + pnp2110_map.virt = (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE); + if (!pnp2110_map.virt) { + printk("Failed to ioremap flash device\n"); + return -ENOMEM; + } + pnp2110_map.cached = __ioremap(pnp2110_map.phys, WINDOW_SIZE, L_PTE_CACHEABLE, 1); + if (!pnp2110_map.cached) + printk(KERN_WARNING "Failed to ioremap cached %s\n", pnp2110_map.name); + + /* Use the default flash access functions */ + simple_map_init(&pnp2110_map); + + /* MTD probing */ + printk( "Probing PNP2110 flash at physical address 0x%08x (%d-bit bankwidth)\n", + WINDOW_ADDR, pnp2110_map.bankwidth * 8 ); + mymtd = do_map_probe("cfi_probe", &pnp2110_map); + if (!mymtd) { + iounmap((void *)pnp2110_map.virt); + if (pnp2110_map.cached) + iounmap(pnp2110_map.cached); + return -EIO; + } + mymtd->owner = THIS_MODULE; + + /* Parse partitions */ + if (parsed_nr_parts > 0) { + parts = parsed_parts; + nb_parts = parsed_nr_parts; + } else { + parts = pnp2110_partitions; + nb_parts = NB_OF(pnp2110_partitions); + } + if (nb_parts) { + printk(KERN_NOTICE "Using %s partition definition\n", part_type); + add_mtd_partitions(mymtd, parts, nb_parts); + } else { + add_mtd_device(mymtd); + } + + pnp2110_set_vpp(&pnp2110_map, 0); + GPDR(PNP2110_VPP_GPIO) |= GPIO_bit(PNP2110_VPP_GPIO); /* output */ + + return 0; +} + +static void __exit cleanup_pnp2110(void) +{ + GPDR(16) &= ~GPIO_bit(16); /* input */ + + if (mymtd) { + del_mtd_partitions(mymtd); + map_destroy(mymtd); + if (parsed_parts) + kfree(parsed_parts); + } + if (pnp2110_map.map_priv_1) + iounmap((void *)pnp2110_map.map_priv_1); + + return; +} + +module_init(init_pnp2110); +module_exit(cleanup_pnp2110); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Marco Hasewinkel, SSV; Robert Schwebel, Pengutronix"); +MODULE_DESCRIPTION("MTD map driver for SSV PNP/2110"); + diff -x .svn -urN linux-2.6.8-rc2/drivers/net/arm/Makefile linux-2.6.8-rc2-pnp1/drivers/net/arm/Makefile --- linux-2.6.8-rc2/drivers/net/arm/Makefile 2004-06-16 07:19:37.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/net/arm/Makefile 2004-07-27 14:01:32.000000000 +0200 @@ -8,3 +8,4 @@ obj-$(CONFIG_ARM_ETHERH) += etherh.o obj-$(CONFIG_ARM_ETHER3) += ether3.o obj-$(CONFIG_ARM_ETHER1) += ether1.o + diff -x .svn -urN linux-2.6.8-rc2/drivers/net/cirrus.c linux-2.6.8-rc2-pnp1/drivers/net/cirrus.c --- linux-2.6.8-rc2/drivers/net/cirrus.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/cirrus.c 2004-07-27 14:01:15.000000000 +0200 @@ -0,0 +1,704 @@ + +/* + * linux/drivers/net/cirrus.c + * + * Author: Abraham van der Merwe + * + * A Cirrus Logic CS8900A driver for Linux + * based on the cs89x0 driver written by Russell Nelson, + * Donald Becker, and others. + * + * This source code is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +/* + * At the moment the driver does not support memory mode operation. + * It is trivial to implement this, but not worth the effort. + */ + +/* + * TODO: + * + * 1. If !ready in send_start(), queue buffer and send it in interrupt handler + * when we receive a BufEvent with Rdy4Tx, send it again. dangerous! + * 2. how do we prevent interrupt handler destroying integrity of get_stats()? + * 3. Change reset code to check status. + * 4. Implement set_mac_address and remove fake mac address + * 5. Link status detection stuff + * 6. Write utility to write EEPROM, do self testing, etc. + * 7. Implement DMA routines (I need a board w/ DMA support for that) + * 8. Power management + * 9. Add support for multiple ethernet chips + * 10. Add support for other cs89xx chips (need hardware for that) + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "cirrus.h" + +/* #define DEBUG */ +/* #define FULL_DUPLEX */ + +#if 0 +//#elif CONFIG_ARCH_CSB226 +# define CIRRUS_DEFAULT_IO 0xF8000300 +# define CIRRUS_DEFAULT_IRQ IRQ_GPIO(14) + /* PTX: uggly hack... */ +# define CS8900_OFF 0x04 +# define CS8900_PPTR *(volatile u32 *)(CIRRUS_DEFAULT_IO+0x05*CS8900_OFF) +# define CS8900_PDATA *(volatile u32 *)(CIRRUS_DEFAULT_IO+0x06*CS8900_OFF) +//#else +# define CIRRUS_DEFAULT_IO 0 +# define CIRRUS_DEFAULT_IRQ 0 +#endif + +typedef struct { + struct net_device_stats stats; + u16 txlen; +} cirrus_t; + +typedef struct { + u16 io_base; /* I/O Base Address */ + u16 irq; /* Interrupt Number */ + u16 dma; /* DMA Channel Numbers */ + u32 mem_base; /* Memory Base Address */ + u32 rom_base; /* Boot PROM Base Address */ + u32 rom_mask; /* Boot PROM Address Mask */ + u8 mac[6]; /* Individual Address */ +} cirrus_eeprom_t; + +/* + * I/O routines + */ + +static inline u16 cirrus_read (struct net_device *dev,u16 reg) +{ + CIRRUS_outw (reg, dev->base_addr, PP_Address); + return (CIRRUS_inw (dev->base_addr, PP_Data)); +} + +static inline void cirrus_write (struct net_device *dev,u16 reg,u16 value) +{ + CIRRUS_outw (reg, dev->base_addr, PP_Address); + CIRRUS_outw (value, dev->base_addr, PP_Data); +} + +static inline void cirrus_set (struct net_device *dev,u16 reg,u16 value) +{ + cirrus_write (dev,reg,cirrus_read (dev,reg) | value); +} + +static inline void cirrus_clear (struct net_device *dev,u16 reg,u16 value) +{ + cirrus_write (dev,reg,cirrus_read (dev,reg) & ~value); +} + +static inline void cirrus_frame_read (struct net_device *dev,struct sk_buff *skb,u16 length) +{ + CIRRUS_insw (dev->base_addr, 0, skb_put (skb,length), (length + 1) / 2); +} + +static inline void cirrus_frame_write (struct net_device *dev,struct sk_buff *skb) +{ + CIRRUS_outsw (dev->base_addr, 0, skb->data, (skb->len + 1) / 2); +} + +/* + * Debugging functions + */ + +#ifdef DEBUG +static inline int printable (int c) +{ + return ((c >= 32 && c <= 126) || + (c >= 174 && c <= 223) || + (c >= 242 && c <= 243) || + (c >= 252 && c <= 253)); +} + +static void dump16 (struct net_device *dev,const u8 *s,size_t len) +{ + int i; + char str[128]; + + if (!len) return; + + *str = '\0'; + + for (i = 0; i < len; i++) { + if (i && !(i % 4)) strcat (str," "); + sprintf (str,"%s%.2x ",str,s[i]); + } + + for ( ; i < 16; i++) { + if (i && !(i % 4)) strcat (str," "); + strcat (str," "); + } + + strcat (str," "); + for (i = 0; i < len; i++) sprintf (str,"%s%c",str,printable (s[i]) ? s[i] : '.'); + + printk (KERN_DEBUG "%s: %s\n",dev->name,str); +} + +static void hexdump (struct net_device *dev,const void *ptr,size_t size) +{ + const u8 *s = (u8 *) ptr; + int i; + for (i = 0; i < size / 16; i++, s += 16) dump16 (dev,s,16); + dump16 (dev,s,size % 16); +} + +static void dump_packet (struct net_device *dev,struct sk_buff *skb,const char *type) +{ + printk (KERN_INFO "%s: %s %d byte frame %.2x:%.2x:%.2x:%.2x:%.2x:%.2x to %.2x:%.2x:%.2x:%.2x:%.2x:%.2x type %.4x\n", + dev->name, + type, + skb->len, + skb->data[0],skb->data[1],skb->data[2],skb->data[3],skb->data[4],skb->data[5], + skb->data[6],skb->data[7],skb->data[8],skb->data[9],skb->data[10],skb->data[11], + (skb->data[12] << 8) | skb->data[13]); + if (skb->len < 0x100) hexdump (dev,skb->data,skb->len); +} +#endif /* #ifdef DEBUG */ + +/* + * Driver functions + */ + +static void cirrus_receive (struct net_device *dev) +{ + cirrus_t *priv = (cirrus_t *) dev->priv; + struct sk_buff *skb; + u16 status,length; + + status = cirrus_read (dev,PP_RxStatus); + length = cirrus_read (dev,PP_RxLength); + + if (!(status & RxOK)) { + priv->stats.rx_errors++; + if ((status & (Runt | Extradata))) priv->stats.rx_length_errors++; + if ((status & CRCerror)) priv->stats.rx_crc_errors++; + return; + } + + if ((skb = dev_alloc_skb (length + 4)) == NULL) { + priv->stats.rx_dropped++; + return; + } + + skb->dev = dev; + skb_reserve (skb,2); + + cirrus_frame_read (dev,skb,length); + +#ifdef DEBUG + dump_packet (dev,skb,"recv"); +#endif /* #ifdef DEBUG */ + + skb->protocol = eth_type_trans (skb,dev); + + netif_rx (skb); + dev->last_rx = jiffies; + + priv->stats.rx_packets++; + priv->stats.rx_bytes += length; +} + +static int cirrus_send_start (struct sk_buff *skb,struct net_device *dev) +{ + cirrus_t *priv = (cirrus_t *) dev->priv; + u16 status; + + netif_stop_queue (dev); + + cirrus_write (dev,PP_TxCMD,TxStart (After5)); + cirrus_write (dev,PP_TxLength,skb->len); + + status = cirrus_read (dev,PP_BusST); + + if ((status & TxBidErr)) { + printk (KERN_WARNING "%s: Invalid frame size %d!\n",dev->name,skb->len); + priv->stats.tx_errors++; + priv->stats.tx_aborted_errors++; + priv->txlen = 0; + return (1); + } + + if (!(status & Rdy4TxNOW)) { + printk (KERN_WARNING "%s: Transmit buffer not free!\n",dev->name); + priv->stats.tx_errors++; + priv->txlen = 0; + /* FIXME: store skb and send it in interrupt handler */ + return (1); + } + + cirrus_frame_write (dev,skb); + +#ifdef DEBUG + dump_packet (dev,skb,"send"); +#endif /* #ifdef DEBUG */ + + dev->trans_start = jiffies; + + dev_kfree_skb (skb); + + priv->txlen = skb->len; + + return (0); +} + +static irqreturn_t cirrus_interrupt (int irq,void *id,struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *) id; + cirrus_t *priv; + u16 status; + + int handled = 0; + + if (dev->priv == NULL) { + printk (KERN_WARNING "%s: irq %d for unknown device.\n",dev->name,irq); + handled = 1; + return IRQ_RETVAL(handled); + } + + priv = (cirrus_t *) dev->priv; + + while ((status = cirrus_read (dev,PP_ISQ))) { + switch (RegNum (status)) { + case RxEvent: + cirrus_receive (dev); + handled = 1; + break; + + case TxEvent: + priv->stats.collisions += ColCount (cirrus_read (dev,PP_TxCOL)); + if (!(RegContent (status) & TxOK)) { + priv->stats.tx_errors++; + if ((RegContent (status) & Out_of_window)) priv->stats.tx_window_errors++; + if ((RegContent (status) & Jabber)) priv->stats.tx_aborted_errors++; + break; + } else if (priv->txlen) { + priv->stats.tx_packets++; + priv->stats.tx_bytes += priv->txlen; + } + priv->txlen = 0; + netif_wake_queue (dev); + handled = 1; + break; + + case BufEvent: + if ((RegContent (status) & RxMiss)) { + u16 missed = MissCount (cirrus_read (dev,PP_RxMISS)); + priv->stats.rx_errors += missed; + priv->stats.rx_missed_errors += missed; + } + if ((RegContent (status) & TxUnderrun)) { + priv->stats.tx_errors++; + priv->stats.tx_fifo_errors++; + } + /* FIXME: if Rdy4Tx, transmit last sent packet (if any) */ + priv->txlen = 0; + netif_wake_queue (dev); + handled = 1; + break; + + case TxCOL: + priv->stats.collisions += ColCount (cirrus_read (dev,PP_TxCOL)); + handled = 1; + break; + + case RxMISS: + status = MissCount (cirrus_read (dev,PP_RxMISS)); + priv->stats.rx_errors += status; + priv->stats.rx_missed_errors += status; + handled = 1; + break; + } + } + + return IRQ_RETVAL(handled); +} + +static void cirrus_transmit_timeout (struct net_device *dev) +{ + cirrus_t *priv = (cirrus_t *) dev->priv; + priv->stats.tx_errors++; + priv->stats.tx_heartbeat_errors++; + priv->txlen = 0; + netif_wake_queue (dev); +} + +static int cirrus_start (struct net_device *dev) +{ + int result; + + /* valid ethernet address? */ + if (!is_valid_ether_addr(dev->dev_addr)) { + printk(KERN_ERR "%s: invalid ethernet MAC address\n",dev->name); + return (-EINVAL); + } + + /* install interrupt handler */ + printk("%s: requesting interrupt %i\n", __FUNCTION__, dev->irq); + if ((result = request_irq (dev->irq,&cirrus_interrupt,0,dev->name,dev)) < 0) { + printk (KERN_ERR "%s: could not register interrupt %d\n",dev->name,dev->irq); + return (result); + } + +#if defined(CONFIG_ARCH_CSB226) + set_irq_type(dev->irq, IRQT_RISING); +#endif + + /* enable the ethernet controller */ + cirrus_set (dev,PP_RxCFG,RxOKiE | BufferCRC | CRCerroriE | RuntiE | ExtradataiE); + cirrus_set (dev,PP_RxCTL,RxOKA | IndividualA | BroadcastA); + cirrus_set (dev,PP_TxCFG,TxOKiE | Out_of_windowiE | JabberiE); + cirrus_set (dev,PP_BufCFG,Rdy4TxiE | RxMissiE | TxUnderruniE | TxColOvfiE | MissOvfloiE); + cirrus_set (dev,PP_LineCTL,SerRxON | SerTxON); + cirrus_set (dev,PP_BusCTL,EnableRQ); + +#ifdef FULL_DUPLEX + cirrus_set (dev,PP_TestCTL,FDX); +#endif /* #ifdef FULL_DUPLEX */ + + /* start the queue */ + netif_start_queue (dev); + + MOD_INC_USE_COUNT; + + return (0); +} + +static int cirrus_stop (struct net_device *dev) +{ + /* disable ethernet controller */ + cirrus_write (dev,PP_BusCTL,0); + cirrus_write (dev,PP_TestCTL,0); + cirrus_write (dev,PP_SelfCTL,0); + cirrus_write (dev,PP_LineCTL,0); + cirrus_write (dev,PP_BufCFG,0); + cirrus_write (dev,PP_TxCFG,0); + cirrus_write (dev,PP_RxCTL,0); + cirrus_write (dev,PP_RxCFG,0); + + /* uninstall interrupt handler */ + free_irq (dev->irq,dev); + + /* stop the queue */ + netif_stop_queue (dev); + + MOD_DEC_USE_COUNT; + + return (0); +} + +static int cirrus_set_mac_address (struct net_device *dev, void *p) +{ + struct sockaddr *addr = (struct sockaddr *)p; + int i; + + if (netif_running(dev)) + return -EBUSY; + + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + + /* configure MAC address */ + for (i = 0; i < ETH_ALEN; i += 2) + cirrus_write (dev,PP_IA + i,dev->dev_addr[i] | (dev->dev_addr[i + 1] << 8)); + + return 0; +} + +static struct net_device_stats *cirrus_get_stats (struct net_device *dev) +{ + cirrus_t *priv = (cirrus_t *) dev->priv; + return (&priv->stats); +} + +static void cirrus_set_receive_mode (struct net_device *dev) +{ + if ((dev->flags & IFF_PROMISC)) + cirrus_set (dev,PP_RxCTL,PromiscuousA); + else + cirrus_clear (dev,PP_RxCTL,PromiscuousA); + + if ((dev->flags & IFF_ALLMULTI) && dev->mc_list) + cirrus_set (dev,PP_RxCTL,MulticastA); + else + cirrus_clear (dev,PP_RxCTL,MulticastA); +} + +static int cirrus_eeprom_wait (struct net_device *dev) +{ + int i; + + for (i = 0; i < 200; i++) { + if (!(cirrus_read (dev,PP_SelfST) & SIBUSY)) + return (0); + udelay (1); + } + + return (-1); +} + +static int cirrus_eeprom_read (struct net_device *dev,u16 *value,u16 offset) +{ + if (cirrus_eeprom_wait (dev) < 0) + return (-1); + + cirrus_write (dev,PP_EEPROMCommand,offset | EEReadRegister); + + if (cirrus_eeprom_wait (dev) < 0) + return (-1); + + *value = cirrus_read (dev,PP_EEPROMData); + + return (0); +} + +static int cirrus_eeprom (struct net_device *dev,cirrus_eeprom_t *eeprom) +{ + u16 offset,buf[16],*word; + u8 checksum = 0,*byte; + + if (cirrus_eeprom_read (dev,buf,0) < 0) { + read_timed_out: + printk (KERN_DEBUG "%s: EEPROM read timed out\n",dev->name); + return (-ETIMEDOUT); + } + + if ((buf[0] >> 8) != 0xa1) { + printk (KERN_DEBUG "%s: No EEPROM present\n",dev->name); + return (-ENODEV); + } + + if ((buf[0] & 0xff) < sizeof (buf)) { + eeprom_too_small: + printk (KERN_DEBUG "%s: EEPROM too small\n",dev->name); + return (-ENODEV); + } + + for (offset = 1; offset < (buf[0] & 0xff); offset++) { + if (cirrus_eeprom_read (dev,buf + offset,offset) < 0) + goto read_timed_out; + + if (buf[offset] == 0xffff) + goto eeprom_too_small; + } + + if (buf[1] != 0x2020) { + printk (KERN_DEBUG "%s: Group Header #1 mismatch\n",dev->name); + return (-EIO); + } + + if (buf[5] != 0x502c) { + printk (KERN_DEBUG "%s: Group Header #2 mismatch\n",dev->name); + return (-EIO); + } + + if (buf[12] != 0x2158) { + printk (KERN_DEBUG "%s: Group Header #3 mismatch\n",dev->name); + return (-EIO); + } + + eeprom->io_base = buf[2]; + eeprom->irq = buf[3]; + eeprom->dma = buf[4]; + eeprom->mem_base = (buf[7] << 16) | buf[6]; + eeprom->rom_base = (buf[9] << 16) | buf[8]; + eeprom->rom_mask = (buf[11] << 16) | buf[10]; + + word = (u16 *) eeprom->mac; + for (offset = 0; offset < 3; offset++) word[offset] = buf[13 + offset]; + + byte = (u8 *) buf; + for (offset = 0; offset < sizeof (buf); offset++) checksum += byte[offset]; + + if (cirrus_eeprom_read (dev,&offset,0x10) < 0) + goto read_timed_out; + + if ((offset >> 8) != (u8) (0x100 - checksum)) { + printk (KERN_DEBUG "%s: Checksum mismatch (expected 0x%.2x, got 0x%.2x instead\n", + dev->name, + (u8) (0x100 - checksum), + offset >> 8); + return (-EIO); + } + + return (0); +} + +/* + * Architecture dependant code + */ + +#ifdef CONFIG_SA1100_FRODO +static void frodo_reset (struct net_device *dev) +{ + int i; + volatile u16 value; + + /* reset ethernet controller */ + FRODO_CPLD_ETHERNET |= FRODO_ETH_RESET; + mdelay (50); + FRODO_CPLD_ETHERNET &= ~FRODO_ETH_RESET; + mdelay (50); + + /* we tied SBHE to CHIPSEL, so each memory access ensure the chip is in 16-bit mode */ + for (i = 0; i < 3; i++) value = cirrus_read (dev,0); + + /* FIXME: poll status bit */ +} +#endif /* #ifdef CONFIG_SA1100_FRODO */ + +/* + * Driver initialization routines + */ + +static int io = 0; +static int irq = 0; + +int __init cirrus_probe (struct net_device *dev) +{ + static cirrus_t priv; + int i,result; + u16 value; + cirrus_eeprom_t eeprom; + + printk ("Cirrus Logic CS8900A driver for Linux (V0.02)\n"); + + memset (&priv,0,sizeof (cirrus_t)); + + ether_setup (dev); + + dev->open = cirrus_start; + dev->stop = cirrus_stop; + dev->hard_start_xmit = cirrus_send_start; + dev->get_stats = cirrus_get_stats; + dev->set_multicast_list = cirrus_set_receive_mode; + dev->set_mac_address = cirrus_set_mac_address; + dev->tx_timeout = cirrus_transmit_timeout; + dev->watchdog_timeo = HZ; + + /* hack!! */ // 00:05:5D:DD:81:18 + dev->dev_addr[0] = 0x00; + dev->dev_addr[1] = 0x00; + dev->dev_addr[2] = 0x02; + dev->dev_addr[3] = 0x50; + dev->dev_addr[4] = 0x10; + dev->dev_addr[5] = 0x08; + + dev->if_port = IF_PORT_10BASET; + dev->priv = (void *) &priv; + + SET_MODULE_OWNER (dev); + + dev->base_addr = CIRRUS_IOADDR; + dev->irq = CIRRUS_IRQ; + + /* module parameters override everything */ + if (io > 0) dev->base_addr = io; + if (irq > 0) dev->irq = irq; + + if (!dev->base_addr) { + printk (KERN_ERR + "%s: No default I/O base address defined. Use io=... or\n" + "%s: define CIRRUS_DEFAULT_IO for your platform\n", + dev->name,dev->name); + return (-EINVAL); + } + + if (!dev->irq) { + printk (KERN_ERR + "%s: No default IRQ number defined. Use irq=... or\n" + "%s: define CIRRUS_DEFAULT_IRQ for your platform\n", + dev->name,dev->name); + return (-EINVAL); + } + + if (!request_region (dev->base_addr,16,dev->name)) { + printk (KERN_ERR "%s: can't get I/O port address 0x%lx\n",dev->name,dev->base_addr); + return -EBUSY; + } + +#ifdef CONFIG_SA1100_FRODO + frodo_reset (dev); +#endif /* #ifdef CONFIG_SA1100_FRODO */ + + /* if an EEPROM is present, use it's MAC address */ + if (!cirrus_eeprom (dev,&eeprom)) + for (i = 0; i < 6; i++) + dev->dev_addr[i] = eeprom.mac[i]; + + /* verify EISA registration number for Cirrus Logic */ + if ((value = cirrus_read (dev,PP_ProductID)) != EISA_REG_CODE) { + printk (KERN_ERR "%s: incorrect signature 0x%.4x\n",dev->name,value); + return (-ENXIO); + } + + /* verify chip version */ + value = cirrus_read (dev,PP_ProductID + 2); + if (VERSION (value) != CS8900A) { + printk (KERN_ERR "%s: unknown chip version 0x%.8x\n",dev->name,VERSION (value)); + return (-ENXIO); + } + printk (KERN_INFO "%s: CS8900A rev %c detected\n",dev->name,'B' + REVISION (value) - REV_B); + + /* setup interrupt number */ + cirrus_write (dev,PP_IntNum,0); + + /* configure MAC address */ + for (i = 0; i < ETH_ALEN; i += 2) + cirrus_write (dev,PP_IA + i,dev->dev_addr[i] | (dev->dev_addr[i + 1] << 8)); + + return (0); +} + +EXPORT_NO_SYMBOLS; + +static struct net_device dev; + +static int __init cirrus_init (void) +{ + memset (&dev,0,sizeof (struct net_device)); + dev.init = cirrus_probe; + return (register_netdev (&dev)); +} + +static void __exit cirrus_cleanup (void) +{ + release_region (dev.base_addr,16); + unregister_netdev (&dev); +} + +MODULE_AUTHOR ("Abraham van der Merwe "); +MODULE_DESCRIPTION ("Cirrus Logic CS8900A driver for Linux (V0.02)"); +MODULE_LICENSE ("GPL"); +MODULE_PARM_DESC (io,"I/O Base Address"); +MODULE_PARM (io,"i"); +MODULE_PARM_DESC (irq,"IRQ Number"); +MODULE_PARM (irq,"i"); + +module_init (cirrus_init); +module_exit (cirrus_cleanup); + diff -x .svn -urN linux-2.6.8-rc2/drivers/net/cirrus.h linux-2.6.8-rc2-pnp1/drivers/net/cirrus.h --- linux-2.6.8-rc2/drivers/net/cirrus.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/cirrus.h 2004-07-27 14:01:15.000000000 +0200 @@ -0,0 +1,309 @@ +#ifndef CIRRUS_H +#define CIRRUS_H + +/* + * linux/drivers/net/cirrus.h + * + * Author: Abraham van der Merwe + * + * A Cirrus Logic CS8900A driver for Linux + * based on the cs89x0 driver written by Russell Nelson, + * Donald Becker, and others. + * + * This source code is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +/* + * Ports + */ + +#define PP_Address 0x0a /* PacketPage Pointer Port (Section 4.10.10) */ +#define PP_Data 0x0c /* PacketPage Data Port (Section 4.10.10) */ + +/* + * Registers + */ + +#define PP_ProductID 0x0000 /* Section 4.3.1 Product Identification Code */ +#define PP_MemBase 0x002c /* Section 4.9.2 Memory Base Address Register */ +#define PP_IntNum 0x0022 /* Section 3.2.3 Interrupt Number */ +#define PP_EEPROMCommand 0x0040 /* Section 4.3.11 EEPROM Command */ +#define PP_EEPROMData 0x0042 /* Section 4.3.12 EEPROM Data */ +#define PP_RxCFG 0x0102 /* Section 4.4.6 Receiver Configuration */ +#define PP_RxCTL 0x0104 /* Section 4.4.8 Receiver Control */ +#define PP_TxCFG 0x0106 /* Section 4.4.9 Transmit Configuration */ +#define PP_BufCFG 0x010a /* Section 4.4.12 Buffer Configuration */ +#define PP_LineCTL 0x0112 /* Section 4.4.16 Line Control */ +#define PP_SelfCTL 0x0114 /* Section 4.4.18 Self Control */ +#define PP_BusCTL 0x0116 /* Section 4.4.20 Bus Control */ +#define PP_TestCTL 0x0118 /* Section 4.4.22 Test Control */ +#define PP_ISQ 0x0120 /* Section 4.4.5 Interrupt Status Queue */ +#define PP_TxEvent 0x0128 /* Section 4.4.10 Transmitter Event */ +#define PP_BufEvent 0x012c /* Section 4.4.13 Buffer Event */ +#define PP_RxMISS 0x0130 /* Section 4.4.14 Receiver Miss Counter */ +#define PP_TxCOL 0x0132 /* Section 4.4.15 Transmit Collision Counter */ +#define PP_SelfST 0x0136 /* Section 4.4.19 Self Status */ +#define PP_BusST 0x0138 /* Section 4.4.21 Bus Status */ +#define PP_TxCMD 0x0144 /* Section 4.4.11 Transmit Command */ +#define PP_TxLength 0x0146 /* Section 4.5.2 Transmit Length */ +#define PP_IA 0x0158 /* Section 4.6.2 Individual Address (IEEE Address) */ +#define PP_RxStatus 0x0400 /* Section 4.7.1 Receive Status */ +#define PP_RxLength 0x0402 /* Section 4.7.1 Receive Length (in bytes) */ +#define PP_RxFrame 0x0404 /* Section 4.7.2 Receive Frame Location */ +#define PP_TxFrame 0x0a00 /* Section 4.7.2 Transmit Frame Location */ + +/* + * Values + */ + +/* PP_IntNum */ +#define INTRQ0 0x0000 +#define INTRQ1 0x0001 +#define INTRQ2 0x0002 +#define INTRQ3 0x0003 + +/* PP_ProductID */ +#define EISA_REG_CODE 0x630e +#define REVISION(x) (((x) & 0x1f00) >> 8) +#define VERSION(x) ((x) & ~0x1f00) + +#define CS8900A 0x0000 +#define REV_B 7 +#define REV_C 8 +#define REV_D 9 + +/* PP_RxCFG */ +#define Skip_1 0x0040 +#define StreamE 0x0080 +#define RxOKiE 0x0100 +#define RxDMAonly 0x0200 +#define AutoRxDMAE 0x0400 +#define BufferCRC 0x0800 +#define CRCerroriE 0x1000 +#define RuntiE 0x2000 +#define ExtradataiE 0x4000 + +/* PP_RxCTL */ +#define IAHashA 0x0040 +#define PromiscuousA 0x0080 +#define RxOKA 0x0100 +#define MulticastA 0x0200 +#define IndividualA 0x0400 +#define BroadcastA 0x0800 +#define CRCerrorA 0x1000 +#define RuntA 0x2000 +#define ExtradataA 0x4000 + +/* PP_TxCFG */ +#define Loss_of_CRSiE 0x0040 +#define SQErroriE 0x0080 +#define TxOKiE 0x0100 +#define Out_of_windowiE 0x0200 +#define JabberiE 0x0400 +#define AnycolliE 0x0800 +#define T16colliE 0x8000 + +/* PP_BufCFG */ +#define SWint_X 0x0040 +#define RxDMAiE 0x0080 +#define Rdy4TxiE 0x0100 +#define TxUnderruniE 0x0200 +#define RxMissiE 0x0400 +#define Rx128iE 0x0800 +#define TxColOvfiE 0x1000 +#define MissOvfloiE 0x2000 +#define RxDestiE 0x8000 + +/* PP_LineCTL */ +#define SerRxON 0x0040 +#define SerTxON 0x0080 +#define AUIonly 0x0100 +#define AutoAUI_10BT 0x0200 +#define ModBackoffE 0x0800 +#define PolarityDis 0x1000 +#define L2_partDefDis 0x2000 +#define LoRxSquelch 0x4000 + +/* PP_SelfCTL */ +#define RESET 0x0040 +#define SWSuspend 0x0100 +#define HWSleepE 0x0200 +#define HWStandbyE 0x0400 +#define HC0E 0x1000 +#define HC1E 0x2000 +#define HCB0 0x4000 +#define HCB1 0x8000 + +/* PP_BusCTL */ +#define ResetRxDMA 0x0040 +#define DMAextend 0x0100 +#define UseSA 0x0200 +#define MemoryE 0x0400 +#define DMABurst 0x0800 +#define IOCHRDYE 0x1000 +#define RxDMAsize 0x2000 +#define EnableRQ 0x8000 + +/* PP_TestCTL */ +#define DisableLT 0x0080 +#define ENDECloop 0x0200 +#define AUIloop 0x0400 +#define DisableBackoff 0x0800 +#define FDX 0x4000 + +/* PP_ISQ */ +#define RegNum(x) ((x) & 0x3f) +#define RegContent(x) ((x) & ~0x3d) + +#define RxEvent 0x0004 +#define TxEvent 0x0008 +#define BufEvent 0x000c +#define RxMISS 0x0010 +#define TxCOL 0x0012 + +/* PP_RxStatus */ +#define IAHash 0x0040 +#define Dribblebits 0x0080 +#define RxOK 0x0100 +#define Hashed 0x0200 +#define IndividualAdr 0x0400 +#define Broadcast 0x0800 +#define CRCerror 0x1000 +#define Runt 0x2000 +#define Extradata 0x4000 + +#define HashTableIndex(x) ((x) >> 0xa) + +/* PP_TxCMD */ +#define After5 0 +#define After381 1 +#define After1021 2 +#define AfterAll 3 +#define TxStart(x) ((x) << 6) + +#define Force 0x0100 +#define Onecoll 0x0200 +#define InhibitCRC 0x1000 +#define TxPadDis 0x2000 + +/* PP_BusST */ +#define TxBidErr 0x0080 +#define Rdy4TxNOW 0x0100 + +/* PP_TxEvent */ +#define Loss_of_CRS 0x0040 +#define SQEerror 0x0080 +#define TxOK 0x0100 +#define Out_of_window 0x0200 +#define Jabber 0x0400 +#define T16coll 0x8000 + +#define TX_collisions(x) (((x) >> 0xb) & ~0x8000) + +/* PP_BufEvent */ +#define SWint 0x0040 +#define RxDMAFrame 0x0080 +#define Rdy4Tx 0x0100 +#define TxUnderrun 0x0200 +#define RxMiss 0x0400 +#define Rx128 0x0800 +#define RxDest 0x8000 + +/* PP_RxMISS */ +#define MissCount(x) ((x) >> 6) + +/* PP_TxCOL */ +#define ColCount(x) ((x) >> 6) + +/* PP_SelfST */ +#define T3VActive 0x0040 +#define INITD 0x0080 +#define SIBUSY 0x0100 +#define EEPROMpresent 0x0200 +#define EEPROMOK 0x0400 +#define ELpresent 0x0800 +#define EEsize 0x1000 + +/* PP_EEPROMCommand */ +#define EEWriteRegister 0x0100 +#define EEReadRegister 0x0200 +#define EEEraseRegister 0x0300 +#define ELSEL 0x0400 + + +/* -------------------- Set Hardware Capabilities for CSB226 -------------- */ + +#if defined(CONFIG_ARCH_CSB226) + +#define CIRRUS_inw(a, r) readw((a) + (r*0x02)) +#define CIRRUS_outw(v, a, r) writew(v, (a) + (r*0x02)) +#define CIRRUS_insw(a, r, p, l) insw((a) + (r*0x02), p, l) +#define CIRRUS_outsw(a, r, p, l) outsw((a) + (r*0x02), p, l) + +#define CIRRUS_IOADDR (CSB226_ETH_VIRT + 0x300) +#define CIRRUS_IRQ CSB226_ETH_IRQ + +/* -------------------- Set Hardware Capabilities for frodo --------------- */ + +#elif defined(CONFIG_SA1100_FRODO) + +#define CIRRUS_inb(a, r) inb((a) + (r)) +#define CIRRUS_inw(a, r) inw((a) + (r)) +#define CIRRUS_outb(v, a, r) outb(v, (a) + (r)) +#define CIRRUS_outw(v, a, r) outw(v, (a) + (r)) +#define CIRRUS_insw(a, r, p, l) insw((a) + (r), p, l) +#define CIRRUS_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#define CIRRUS_IOADDR (FRODO_ETH_IO + 0x300) +#define CIRRUS_IRQ FRODO_ETH_IRQ + +/* -------------------- Set Hardware Capabilities for cerf ---------------- */ + +#elif defined(CONFIG_SA1100_CERF) + +#define CIRRUS_inb(a, r) inb((a) + (r)) +#define CIRRUS_inw(a, r) inw((a) + (r)) +#define CIRRUS_outb(v, a, r) outb(v, (a) + (r)) +#define CIRRUS_outw(v, a, r) outw(v, (a) + (r)) +#define CIRRUS_insw(a, r, p, l) insw((a) + (r), p, l) +#define CIRRUS_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#define CIRRUS_IOADDR (CERF_ETH_IO + 0x300) +#define CIRRUS_IRQ CERF_ETH_IRQ + +/* -------------------- Set Hardware Capabilities for CDB89712 ------------ */ + +#elif defined(CONFIG_ARCH_CDB89712) + +#define CIRRUS_inb(a, r) inb((a) + (r)) +#define CIRRUS_inw(a, r) inw((a) + (r)) +#define CIRRUS_outb(v, a, r) outb(v, (a) + (r)) +#define CIRRUS_outw(v, a, r) outw(v, (a) + (r)) +#define CIRRUS_insw(a, r, p, l) insw((a) + (r), p, l) +#define CIRRUS_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#define CIRRUS_IOADDR (ETHER_BASE + 0x300) +#define CIRRUS_IRQ IRQ_EINT3 + +/* -------------------- ISA ----------------------------------------------- */ + +#elif defined(CONFIG_ISA) + +#define CIRRUS_inb(a, r) inb((a) + (r)) +#define CIRRUS_inw(a, r) inw((a) + (r)) +#define CIRRUS_outb(v, a, r) outb(v, (a) + (r)) +#define CIRRUS_outw(v, a, r) outw(v, (a) + (r)) +#define CIRRUS_insw(a, r, p, l) insw((a) + (r), p, l) +#define CIRRUS_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#define CIRRUS_IOADDR 0 +#define CIRRUS_IRQ 0 + +#else +#error "FIXME..." +#endif + +#endif /* #ifndef CIRRUS_H */ + diff -x .svn -urN linux-2.6.8-rc2/drivers/net/cs89x0.c linux-2.6.8-rc2-pnp1/drivers/net/cs89x0.c --- linux-2.6.8-rc2/drivers/net/cs89x0.c 2004-07-27 14:08:05.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/net/cs89x0.c 2004-07-27 14:01:27.000000000 +0200 @@ -162,6 +162,18 @@ static unsigned int netcard_portlist[] __initdata = { 0x0300, 0}; static unsigned int cs8900_irq_map[] = {1,0,0,0}; +#elif defined(CONFIG_ARCH_CSB226) +static unsigned int netcard_portlist[] __initdata = + { CSB226_ETH_VIRT+0x0300+1, 0}; +static unsigned int cs8900_irq_map[] = {37,0,0,0}; +#undef inw +#define inw(a,r) readw((a) + (r*0x02)) +#undef outw +#define outw(v, a, r) writew(v, (a) + (r*0x02)) +#undef insw +#define insw(a, r, p, l) insw((a) + (r*0x02), p, l) +#undef outsw +#define outsw(a, r, p, l) outsw((a) + (r*0x02), p, l) #else static unsigned int netcard_portlist[] __initdata = { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; @@ -457,7 +469,7 @@ ioaddr &= ~3; outw(PP_ChipID, ioaddr + ADD_PORT); } -printk("PP_addr=0x%x\n", inw(ioaddr + ADD_PORT)); + printk("PP_addr=0x%x\n", inw(ioaddr + ADD_PORT)); if (inw(ioaddr + DATA_PORT) != CHIP_EISA_ID_SIG) { printk(KERN_ERR "%s: incorrect signature 0x%x\n", diff -x .svn -urN linux-2.6.8-rc2/drivers/net/cs89x0-old.c linux-2.6.8-rc2-pnp1/drivers/net/cs89x0-old.c --- linux-2.6.8-rc2/drivers/net/cs89x0-old.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/cs89x0-old.c 2004-07-27 14:01:29.000000000 +0200 @@ -0,0 +1,1831 @@ +/* cs89x0.c: A Crystal Semiconductor (Now Cirrus Logic) CS89[02]0 + * driver for linux. + */ + +/* + Written 1996 by Russell Nelson, with reference to skeleton.c + written 1993-1994 by Donald Becker. + + This software may be used and distributed according to the terms + of the GNU General Public License, incorporated herein by reference. + + The author may be reached at nelson@crynwr.com, Crynwr + Software, 521 Pleasant Valley Rd., Potsdam, NY 13676 + + Changelog: + + Mike Cruse : mcruse@cti-ltd.com + : Changes for Linux 2.0 compatibility. + : Added dev_id parameter in net_interrupt(), + : request_irq() and free_irq(). Just NULL for now. + + Mike Cruse : Added MOD_INC_USE_COUNT and MOD_DEC_USE_COUNT macros + : in net_open() and net_close() so kerneld would know + : that the module is in use and wouldn't eject the + : driver prematurely. + + Mike Cruse : Rewrote init_module() and cleanup_module using 8390.c + : as an example. Disabled autoprobing in init_module(), + : not a good thing to do to other devices while Linux + : is running from all accounts. + + Russ Nelson : Jul 13 1998. Added RxOnly DMA support. + + Melody Lee : Aug 10 1999. Changes for Linux 2.2.5 compatibility. + : email: ethernet@crystal.cirrus.com + + Alan Cox : Removed 1.2 support, added 2.1 extra counters. + + Andrew Morton : andrewm@uow.edu.au + : Kernel 2.3.48 + : Handle kmalloc() failures + : Other resource allocation fixes + : Add SMP locks + : Integrate Russ Nelson's ALLOW_DMA functionality back in. + : If ALLOW_DMA is true, make DMA runtime selectable + : Folded in changes from Cirrus (Melody Lee + : ) + : Don't call netif_wake_queue() in net_send_packet() + : Fixed an out-of-mem bug in dma_rx() + : Updated Documentation/cs89x0.txt + + Andrew Morton : andrewm@uow.edu.au / Kernel 2.3.99-pre1 + : Use skb_reserve to longword align IP header (two places) + : Remove a delay loop from dma_rx() + : Replace '100' with HZ + : Clean up a couple of skb API abuses + : Added 'cs89x0_dma=N' kernel boot option + : Correctly initialise lp->lock in non-module compile + + Andrew Morton : andrewm@uow.edu.au / Kernel 2.3.99-pre4-1 + : MOD_INC/DEC race fix (see + : http://www.uwsg.indiana.edu/hypermail/linux/kernel/0003.3/1532.html) + + Andrew Morton : andrewm@uow.edu.au / Kernel 2.4.0-test7-pre2 + : Enhanced EEPROM support to cover more devices, + : abstracted IRQ mapping to support CONFIG_ARCH_CLPS7500 arch + : (Jason Gunthorpe ) + + Andrew Morton : Kernel 2.4.0-test11-pre4 + : Use dev->name in request_*() (Andrey Panin) + : Fix an error-path memleak in init_module() + : Preserve return value from request_irq() + : Fix type of `media' module parm (Keith Owens) + : Use SET_MODULE_OWNER() + : Tidied up strange request_irq() abuse in net_open(). + + Andrew Morton : Kernel 2.4.3-pre1 + : Request correct number of pages for DMA (Hugh Dickens) + : Select PP_ChipID _after_ unregister_netdev in cleanup_module() + : because unregister_netdev() calls get_stats. + : Make `version[]' __initdata + : Uninlined the read/write reg/word functions. + + Oskar Schirmer : oskar@scara.com + : HiCO.SH4 (superh) support added (irq#1, cs89x0_media=) + +*/ + +/* Always include 'config.h' first in case the user wants to turn on + or override something. */ +#include +#include +#include + +/* + * Set this to zero to disable DMA code + * + * Note that even if DMA is turned off we still support the 'dma' and 'use_dma' + * module options so we don't break any startup scripts. + */ +#define ALLOW_DMA 1 + +/* + * Set this to zero to remove all the debug statements via + * dead code elimination + */ +#define DEBUGGING 1 + +/* + Sources: + + Crynwr packet driver epktisa. + + Crystal Semiconductor data sheets. + +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if ALLOW_DMA +#include +#endif +#include +#include + +#include +#include +#include + +#include "cs89x0.h" + +static char version[] __initdata = +"cs89x0.c: v2.4.3-pre1 Russell Nelson , Andrew Morton \n"; + +/* First, a few definitions that the brave might change. + A zero-terminated list of I/O addresses to be probed. Some special flags.. + Addr & 1 = Read back the address port, look for signature and reset + the page window before probing + Addr & 3 = Reset the page window and probe + The CLPS eval board has the Cirrus chip at 0x80090300, in ARM IO space, + but it is possible that a Cirrus board could be plugged into the ISA + slots. */ +/* The cs8900 has 4 IRQ pins, software selectable. cs8900_irq_map maps + them to system IRQ numbers. This mapping is card specific and is set to + the configuration of the Cirrus Eval board for this chip. */ +#ifdef CONFIG_ARCH_CLPS7500 +static unsigned int netcard_portlist[] __initdata = + { 0x80090303, 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; +static unsigned int cs8900_irq_map[] = {12,0,0,0}; +#elif defined(CONFIG_SH_HICOSH4) +static unsigned int netcard_portlist[] __initdata = + { 0x0300, 0}; +static unsigned int cs8900_irq_map[] = {1,0,0,0}; +#else +static unsigned int netcard_portlist[] __initdata = + { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; +static unsigned int cs8900_irq_map[] = {10,11,12,5}; +#endif + +#if DEBUGGING +static unsigned int net_debug = DEBUGGING; +#else +#define net_debug 0 /* gcc will remove all the debug code for us */ +#endif + +/* The number of low I/O ports used by the ethercard. */ +#define NETCARD_IO_EXTENT 16 + +/* we allow the user to override various values normally set in the EEPROM */ +#define FORCE_RJ45 0x0001 /* pick one of these three */ +#define FORCE_AUI 0x0002 +#define FORCE_BNC 0x0004 + +#define FORCE_AUTO 0x0010 /* pick one of these three */ +#define FORCE_HALF 0x0020 +#define FORCE_FULL 0x0030 + +/* Information that need to be kept for each board. */ +struct net_local { + struct net_device_stats stats; + int chip_type; /* one of: CS8900, CS8920, CS8920M */ + char chip_revision; /* revision letter of the chip ('A'...) */ + int send_cmd; /* the proper send command: TX_NOW, TX_AFTER_381, or TX_AFTER_ALL */ + int auto_neg_cnf; /* auto-negotiation word from EEPROM */ + int adapter_cnf; /* adapter configuration from EEPROM */ + int isa_config; /* ISA configuration from EEPROM */ + int irq_map; /* IRQ map from EEPROM */ + int rx_mode; /* what mode are we in? 0, RX_MULTCAST_ACCEPT, or RX_ALL_ACCEPT */ + int curr_rx_cfg; /* a copy of PP_RxCFG */ + int linectl; /* either 0 or LOW_RX_SQUELCH, depending on configuration. */ + int send_underrun; /* keep track of how many underruns in a row we get */ + int force; /* force various values; see FORCE* above. */ + spinlock_t lock; +#if ALLOW_DMA + int use_dma; /* Flag: we're using dma */ + int dma; /* DMA channel */ + int dmasize; /* 16 or 64 */ + unsigned char *dma_buff; /* points to the beginning of the buffer */ + unsigned char *end_dma_buff; /* points to the end of the buffer */ + unsigned char *rx_dma_ptr; /* points to the next packet */ +#endif +}; + +/* Index to functions, as function prototypes. */ + +extern int cs89x0_probe(struct net_device *dev); + +static int cs89x0_probe1(struct net_device *dev, int ioaddr); +static int net_open(struct net_device *dev); +static int net_send_packet(struct sk_buff *skb, struct net_device *dev); +static void net_interrupt(int irq, void *dev_id, struct pt_regs *regs); +static void set_multicast_list(struct net_device *dev); +static void net_timeout(struct net_device *dev); +static void net_rx(struct net_device *dev); +static int net_close(struct net_device *dev); +static struct net_device_stats *net_get_stats(struct net_device *dev); +static void reset_chip(struct net_device *dev); +static int get_eeprom_data(struct net_device *dev, int off, int len, int *buffer); +static int get_eeprom_cksum(int off, int len, int *buffer); +static int set_mac_address(struct net_device *dev, void *addr); +static void count_rx_errors(int status, struct net_local *lp); +#if ALLOW_DMA +static void get_dma_channel(struct net_device *dev); +static void release_dma_buff(struct net_local *lp); +#endif + +/* Example routines you must write ;->. */ +#define tx_done(dev) 1 + +/* + * Permit 'cs89x0_dma=N' in the kernel boot environment + */ +#if !defined(MODULE) && (ALLOW_DMA != 0) +static int g_cs89x0_dma; + +static int __init dma_fn(char *str) +{ + g_cs89x0_dma = simple_strtol(str,NULL,0); + return 1; +} + +__setup("cs89x0_dma=", dma_fn); +#endif /* !defined(MODULE) && (ALLOW_DMA != 0) */ + +#ifndef MODULE +static int g_cs89x0_media__force; + +static int __init media_fn(char *str) +{ + if (!strcmp(str, "rj45")) g_cs89x0_media__force = FORCE_RJ45; + else if (!strcmp(str, "aui")) g_cs89x0_media__force = FORCE_AUI; + else if (!strcmp(str, "bnc")) g_cs89x0_media__force = FORCE_BNC; + return 1; +} + +__setup("cs89x0_media=", media_fn); +#endif + + +/* Check for a network adaptor of this type, and return '0' iff one exists. + If dev->base_addr == 0, probe all likely locations. + If dev->base_addr == 1, always return failure. + If dev->base_addr == 2, allocate space for the device and return success + (detachable devices only). + Return 0 on success. + */ + +int __init cs89x0_probe(struct net_device *dev) +{ + int i; + int base_addr = dev ? dev->base_addr : 0; + + SET_MODULE_OWNER(dev); + + if (net_debug) + printk("cs89x0:cs89x0_probe(0x%x)\n", base_addr); + + if (base_addr > 0x1ff) /* Check a single specified location. */ + return cs89x0_probe1(dev, base_addr); + else if (base_addr != 0) /* Don't probe at all. */ + return -ENXIO; + + for (i = 0; netcard_portlist[i]; i++) { + if (cs89x0_probe1(dev, netcard_portlist[i]) == 0) + return 0; + } + printk(KERN_WARNING "cs89x0: no cs8900 or cs8920 detected. Be sure to disable PnP with SETUP\n"); + return -ENODEV; +} + +static int +readreg(struct net_device *dev, int portno) +{ + outw(portno, dev->base_addr + ADD_PORT); + return inw(dev->base_addr + DATA_PORT); +} + +static void +writereg(struct net_device *dev, int portno, int value) +{ + outw(portno, dev->base_addr + ADD_PORT); + outw(value, dev->base_addr + DATA_PORT); +} + +static int +readword(struct net_device *dev, int portno) +{ + return inw(dev->base_addr + portno); +} + +static void +writeword(struct net_device *dev, int portno, int value) +{ + outw(value, dev->base_addr + portno); +} + +static int __init +wait_eeprom_ready(struct net_device *dev) +{ + int timeout = jiffies; + /* check to see if the EEPROM is ready, a timeout is used - + just in case EEPROM is ready when SI_BUSY in the + PP_SelfST is clear */ + while(readreg(dev, PP_SelfST) & SI_BUSY) + if (jiffies - timeout >= 40) + return -1; + return 0; +} + +static int __init +get_eeprom_data(struct net_device *dev, int off, int len, int *buffer) +{ + int i; + + if (net_debug > 3) printk("EEPROM data from %x for %x:\n",off,len); + for (i = 0; i < len; i++) { + if (wait_eeprom_ready(dev) < 0) return -1; + /* Now send the EEPROM read command and EEPROM location to read */ + writereg(dev, PP_EECMD, (off + i) | EEPROM_READ_CMD); + if (wait_eeprom_ready(dev) < 0) return -1; + buffer[i] = readreg(dev, PP_EEData); + if (net_debug > 3) printk("%04x ", buffer[i]); + } + if (net_debug > 3) printk("\n"); + return 0; +} + +static int __init +get_eeprom_cksum(int off, int len, int *buffer) +{ + int i, cksum; + + cksum = 0; + for (i = 0; i < len; i++) + cksum += buffer[i]; + cksum &= 0xffff; + if (cksum == 0) + return 0; + return -1; +} + +/* This is the real probe routine. Linux has a history of friendly device + probes on the ISA bus. A good device probes avoids doing writes, and + verifies that the correct device exists and functions. + Return 0 on success. + */ + +static int __init +cs89x0_probe1(struct net_device *dev, int ioaddr) +{ + struct net_local *lp; + static unsigned version_printed; + int i; + unsigned rev_type = 0; + int eeprom_buff[CHKSUM_LEN]; + int retval; + + /* Initialize the device structure. */ + if (dev->priv == NULL) { + dev->priv = kmalloc(sizeof(struct net_local), GFP_KERNEL); + if (dev->priv == 0) { + retval = -ENOMEM; + goto out; + } + lp = (struct net_local *)dev->priv; + memset(lp, 0, sizeof(*lp)); + spin_lock_init(&lp->lock); +#if !defined(MODULE) && (ALLOW_DMA != 0) + if (g_cs89x0_dma) { + lp->use_dma = 1; + lp->dma = g_cs89x0_dma; + lp->dmasize = 16; /* Could make this an option... */ + } +#endif +#ifndef MODULE + lp->force = g_cs89x0_media__force; +#endif + } + lp = (struct net_local *)dev->priv; + + /* Grab the region so we can find another board if autoIRQ fails. */ + if (!request_region(ioaddr & ~3, NETCARD_IO_EXTENT, dev->name)) { + printk(KERN_ERR "%s: request_region(0x%x, 0x%x) failed\n", + dev->name, ioaddr, NETCARD_IO_EXTENT); + retval = -EBUSY; + goto out1; + } + +#ifdef CONFIG_SH_HICOSH4 + /* truely reset the chip */ + outw(0x0114, ioaddr + ADD_PORT); + outw(0x0040, ioaddr + DATA_PORT); +#endif + + /* if they give us an odd I/O address, then do ONE write to + the address port, to get it back to address zero, where we + expect to find the EISA signature word. An IO with a base of 0x3 + will skip the test for the ADD_PORT. */ + if (ioaddr & 1) { + if (net_debug > 1) + printk(KERN_INFO "%s: odd ioaddr 0x%x\n", dev->name, ioaddr); + if ((ioaddr & 2) != 2) + if ((inw((ioaddr & ~3)+ ADD_PORT) & ADD_MASK) != ADD_SIG) { + printk(KERN_ERR "%s: bad signature 0x%x\n", + dev->name, inw((ioaddr & ~3)+ ADD_PORT)); + retval = -ENODEV; + goto out2; + } + ioaddr &= ~3; + outw(PP_ChipID, ioaddr + ADD_PORT); + } +printk("PP_addr=0x%x\n", inw(ioaddr + ADD_PORT)); + + if (inw(ioaddr + DATA_PORT) != CHIP_EISA_ID_SIG) { + printk(KERN_ERR "%s: incorrect signature 0x%x\n", + dev->name, inw(ioaddr + DATA_PORT)); + retval = -ENODEV; + goto out2; + } + + /* Fill in the 'dev' fields. */ + dev->base_addr = ioaddr; + + /* get the chip type */ + rev_type = readreg(dev, PRODUCT_ID_ADD); + lp->chip_type = rev_type &~ REVISON_BITS; + lp->chip_revision = ((rev_type & REVISON_BITS) >> 8) + 'A'; + + /* Check the chip type and revision in order to set the correct send command + CS8920 revision C and CS8900 revision F can use the faster send. */ + lp->send_cmd = TX_AFTER_381; + if (lp->chip_type == CS8900 && lp->chip_revision >= 'F') + lp->send_cmd = TX_NOW; + if (lp->chip_type != CS8900 && lp->chip_revision >= 'C') + lp->send_cmd = TX_NOW; + + if (net_debug && version_printed++ == 0) + printk(version); + + printk(KERN_INFO "%s: cs89%c0%s rev %c found at %#3lx ", + dev->name, + lp->chip_type==CS8900?'0':'2', + lp->chip_type==CS8920M?"M":"", + lp->chip_revision, + dev->base_addr); + + reset_chip(dev); + + /* Here we read the current configuration of the chip. If there + is no Extended EEPROM then the idea is to not disturb the chip + configuration, it should have been correctly setup by automatic + EEPROM read on reset. So, if the chip says it read the EEPROM + the driver will always do *something* instead of complain that + adapter_cnf is 0. */ + +#ifdef CONFIG_SH_HICOSH4 + if (1) { + /* For the HiCO.SH4 board, things are different: we don't + have EEPROM, but there is some data in flash, so we go + get it there directly (MAC). */ + __u16 *confd; + short cnt; + if (((* (volatile __u32 *) 0xa0013ff0) & 0x00ffffff) + == 0x006c3000) { + confd = (__u16*) 0xa0013fc0; + } else { + confd = (__u16*) 0xa001ffc0; + } + cnt = (*confd++ & 0x00ff) >> 1; + while (--cnt > 0) { + __u16 j = *confd++; + + switch (j & 0x0fff) { + case PP_IA: + for (i = 0; i < ETH_ALEN/2; i++) { + dev->dev_addr[i*2] = confd[i] & 0xFF; + dev->dev_addr[i*2+1] = confd[i] >> 8; + } + break; + } + j = (j >> 12) + 1; + confd += j; + cnt -= j; + } + } else +#endif + + if ((readreg(dev, PP_SelfST) & (EEPROM_OK | EEPROM_PRESENT)) == + (EEPROM_OK|EEPROM_PRESENT)) { + /* Load the MAC. */ + for (i=0; i < ETH_ALEN/2; i++) { + unsigned int Addr; + Addr = readreg(dev, PP_IA+i*2); + dev->dev_addr[i*2] = Addr & 0xFF; + dev->dev_addr[i*2+1] = Addr >> 8; + } + + /* Load the Adapter Configuration. + Note: Barring any more specific information from some + other source (ie EEPROM+Schematics), we would not know + how to operate a 10Base2 interface on the AUI port. + However, since we do read the status of HCB1 and use + settings that always result in calls to control_dc_dc(dev,0) + a BNC interface should work if the enable pin + (dc/dc converter) is on HCB1. It will be called AUI + however. */ + + lp->adapter_cnf = 0; + i = readreg(dev, PP_LineCTL); + /* Preserve the setting of the HCB1 pin. */ + if ((i & (HCB1 | HCB1_ENBL)) == (HCB1 | HCB1_ENBL)) + lp->adapter_cnf |= A_CNF_DC_DC_POLARITY; + /* Save the sqelch bit */ + if ((i & LOW_RX_SQUELCH) == LOW_RX_SQUELCH) + lp->adapter_cnf |= A_CNF_EXTND_10B_2 | A_CNF_LOW_RX_SQUELCH; + /* Check if the card is in 10Base-t only mode */ + if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == 0) + lp->adapter_cnf |= A_CNF_10B_T | A_CNF_MEDIA_10B_T; + /* Check if the card is in AUI only mode */ + if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == AUI_ONLY) + lp->adapter_cnf |= A_CNF_AUI | A_CNF_MEDIA_AUI; + /* Check if the card is in Auto mode. */ + if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == AUTO_AUI_10BASET) + lp->adapter_cnf |= A_CNF_AUI | A_CNF_10B_T | + A_CNF_MEDIA_AUI | A_CNF_MEDIA_10B_T | A_CNF_MEDIA_AUTO; + + if (net_debug > 1) + printk(KERN_INFO "%s: PP_LineCTL=0x%x, adapter_cnf=0x%x\n", + dev->name, i, lp->adapter_cnf); + + /* IRQ. Other chips already probe, see below. */ + if (lp->chip_type == CS8900) + lp->isa_config = readreg(dev, PP_CS8900_ISAINT) & INT_NO_MASK; + + printk( "[Cirrus EEPROM] "); + } + + printk("\n"); + + /* First check to see if an EEPROM is attached. */ +#ifdef CONFIG_SH_HICOSH4 /* no EEPROM on HiCO, don't hazzle with it here */ + if (1) { + printk(KERN_NOTICE "cs89x0: No EEPROM on HiCO.SH4\n"); + } else +#endif + if ((readreg(dev, PP_SelfST) & EEPROM_PRESENT) == 0) + printk(KERN_WARNING "cs89x0: No EEPROM, relying on command line....\n"); + else if (get_eeprom_data(dev, START_EEPROM_DATA,CHKSUM_LEN,eeprom_buff) < 0) { + printk(KERN_WARNING "\ncs89x0: EEPROM read failed, relying on command line.\n"); + } else if (get_eeprom_cksum(START_EEPROM_DATA,CHKSUM_LEN,eeprom_buff) < 0) { + /* Check if the chip was able to read its own configuration starting + at 0 in the EEPROM*/ + if ((readreg(dev, PP_SelfST) & (EEPROM_OK | EEPROM_PRESENT)) != + (EEPROM_OK|EEPROM_PRESENT)) + printk(KERN_WARNING "cs89x0: Extended EEPROM checksum bad and no Cirrus EEPROM, relying on command line\n"); + + } else { + /* This reads an extended EEPROM that is not documented + in the CS8900 datasheet. */ + + /* get transmission control word but keep the autonegotiation bits */ + if (!lp->auto_neg_cnf) lp->auto_neg_cnf = eeprom_buff[AUTO_NEG_CNF_OFFSET/2]; + /* Store adapter configuration */ + if (!lp->adapter_cnf) lp->adapter_cnf = eeprom_buff[ADAPTER_CNF_OFFSET/2]; + /* Store ISA configuration */ + lp->isa_config = eeprom_buff[ISA_CNF_OFFSET/2]; + dev->mem_start = eeprom_buff[PACKET_PAGE_OFFSET/2] << 8; + + /* eeprom_buff has 32-bit ints, so we can't just memcpy it */ + /* store the initial memory base address */ + for (i = 0; i < ETH_ALEN/2; i++) { + dev->dev_addr[i*2] = eeprom_buff[i]; + dev->dev_addr[i*2+1] = eeprom_buff[i] >> 8; + } + if (net_debug > 1) + printk(KERN_DEBUG "%s: new adapter_cnf: 0x%x\n", + dev->name, lp->adapter_cnf); + } + + /* allow them to force multiple transceivers. If they force multiple, autosense */ + { + int count = 0; + if (lp->force & FORCE_RJ45) {lp->adapter_cnf |= A_CNF_10B_T; count++; } + if (lp->force & FORCE_AUI) {lp->adapter_cnf |= A_CNF_AUI; count++; } + if (lp->force & FORCE_BNC) {lp->adapter_cnf |= A_CNF_10B_2; count++; } + if (count > 1) {lp->adapter_cnf |= A_CNF_MEDIA_AUTO; } + else if (lp->force & FORCE_RJ45){lp->adapter_cnf |= A_CNF_MEDIA_10B_T; } + else if (lp->force & FORCE_AUI) {lp->adapter_cnf |= A_CNF_MEDIA_AUI; } + else if (lp->force & FORCE_BNC) {lp->adapter_cnf |= A_CNF_MEDIA_10B_2; } + } + + if (net_debug > 1) + printk(KERN_DEBUG "%s: after force 0x%x, adapter_cnf=0x%x\n", + dev->name, lp->force, lp->adapter_cnf); + + /* FIXME: We don't let you set dc-dc polarity or low RX squelch from the command line: add it here */ + + /* FIXME: We don't let you set the IMM bit from the command line: add it to lp->auto_neg_cnf here */ + + /* FIXME: we don't set the Ethernet address on the command line. Use + ifconfig IFACE hw ether AABBCCDDEEFF */ + + printk(KERN_INFO "cs89x0 media %s%s%s", + (lp->adapter_cnf & A_CNF_10B_T)?"RJ-45,":"", + (lp->adapter_cnf & A_CNF_AUI)?"AUI,":"", + (lp->adapter_cnf & A_CNF_10B_2)?"BNC,":""); + + lp->irq_map = 0xffff; + + /* If this is a CS8900 then no pnp soft */ + if (lp->chip_type != CS8900 && + /* Check if the ISA IRQ has been set */ + (i = readreg(dev, PP_CS8920_ISAINT) & 0xff, + (i != 0 && i < CS8920_NO_INTS))) { + if (!dev->irq) + dev->irq = i; + } else { + i = lp->isa_config & INT_NO_MASK; + if (lp->chip_type == CS8900) { + /* Translate the IRQ using the IRQ mapping table. */ + if (i >= sizeof(cs8900_irq_map)/sizeof(cs8900_irq_map[0])) + printk("\ncs89x0: invalid ISA interrupt number %d\n", i); + else + i = cs8900_irq_map[i]; + + lp->irq_map = CS8900_IRQ_MAP; /* fixed IRQ map for CS8900 */ + } else { + int irq_map_buff[IRQ_MAP_LEN/2]; + + if (get_eeprom_data(dev, IRQ_MAP_EEPROM_DATA, + IRQ_MAP_LEN/2, + irq_map_buff) >= 0) { + if ((irq_map_buff[0] & 0xff) == PNP_IRQ_FRMT) + lp->irq_map = (irq_map_buff[0]>>8) | (irq_map_buff[1] << 8); + } + } + if (!dev->irq) + dev->irq = i; + } + + printk(" IRQ %d", dev->irq); + +#if ALLOW_DMA + if (lp->use_dma) { + get_dma_channel(dev); + printk(", DMA %d", dev->dma); + } + else +#endif + { + printk(", programmed I/O"); + } + + /* print the ethernet address. */ + printk(", MAC"); + for (i = 0; i < ETH_ALEN; i++) + { + printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]); + } + + dev->open = net_open; + dev->stop = net_close; + dev->tx_timeout = net_timeout; + dev->watchdog_timeo = HZ; + dev->hard_start_xmit = net_send_packet; + dev->get_stats = net_get_stats; + dev->set_multicast_list = set_multicast_list; + dev->set_mac_address = set_mac_address; + + /* Fill in the fields of the device structure with ethernet values. */ + ether_setup(dev); + + printk("\n"); + if (net_debug) + printk("cs89x0_probe1() successful\n"); + return 0; +out2: + release_region(ioaddr & ~3, NETCARD_IO_EXTENT); +out1: + kfree(dev->priv); + dev->priv = 0; +out: + return retval; +} + + +/********************************* + * This page contains DMA routines +**********************************/ + +#if ALLOW_DMA + +#define dma_page_eq(ptr1, ptr2) ((long)(ptr1)>>17 == (long)(ptr2)>>17) + +static void +get_dma_channel(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + + if (lp->dma) { + dev->dma = lp->dma; + lp->isa_config |= ISA_RxDMA; + } else { + if ((lp->isa_config & ANY_ISA_DMA) == 0) + return; + dev->dma = lp->isa_config & DMA_NO_MASK; + if (lp->chip_type == CS8900) + dev->dma += 5; + if (dev->dma < 5 || dev->dma > 7) { + lp->isa_config &= ~ANY_ISA_DMA; + return; + } + } + return; +} + +static void +write_dma(struct net_device *dev, int chip_type, int dma) +{ + struct net_local *lp = (struct net_local *)dev->priv; + if ((lp->isa_config & ANY_ISA_DMA) == 0) + return; + if (chip_type == CS8900) { + writereg(dev, PP_CS8900_ISADMA, dma-5); + } else { + writereg(dev, PP_CS8920_ISADMA, dma); + } +} + +static void +set_dma_cfg(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + + if (lp->use_dma) { + if ((lp->isa_config & ANY_ISA_DMA) == 0) { + if (net_debug > 3) + printk("set_dma_cfg(): no DMA\n"); + return; + } + if (lp->isa_config & ISA_RxDMA) { + lp->curr_rx_cfg |= RX_DMA_ONLY; + if (net_debug > 3) + printk("set_dma_cfg(): RX_DMA_ONLY\n"); + } else { + lp->curr_rx_cfg |= AUTO_RX_DMA; /* not that we support it... */ + if (net_debug > 3) + printk("set_dma_cfg(): AUTO_RX_DMA\n"); + } + } +} + +static int +dma_bufcfg(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + if (lp->use_dma) + return (lp->isa_config & ANY_ISA_DMA)? RX_DMA_ENBL : 0; + else + return 0; +} + +static int +dma_busctl(struct net_device *dev) +{ + int retval = 0; + struct net_local *lp = (struct net_local *)dev->priv; + if (lp->use_dma) { + if (lp->isa_config & ANY_ISA_DMA) + retval |= RESET_RX_DMA; /* Reset the DMA pointer */ + if (lp->isa_config & DMA_BURST) + retval |= DMA_BURST_MODE; /* Does ISA config specify DMA burst ? */ + if (lp->dmasize == 64) + retval |= RX_DMA_SIZE_64K; /* did they ask for 64K? */ + retval |= MEMORY_ON; /* we need memory enabled to use DMA. */ + } + return retval; +} + +static void +dma_rx(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + struct sk_buff *skb; + int status, length; + unsigned char *bp = lp->rx_dma_ptr; + + status = bp[0] + (bp[1]<<8); + length = bp[2] + (bp[3]<<8); + bp += 4; + if (net_debug > 5) { + printk( "%s: receiving DMA packet at %lx, status %x, length %x\n", + dev->name, (unsigned long)bp, status, length); + } + if ((status & RX_OK) == 0) { + count_rx_errors(status, lp); + goto skip_this_frame; + } + + /* Malloc up new buffer. */ + skb = dev_alloc_skb(length + 2); + if (skb == NULL) { + if (net_debug) /* I don't think we want to do this to a stressed system */ + printk("%s: Memory squeeze, dropping packet.\n", dev->name); + lp->stats.rx_dropped++; + + /* AKPM: advance bp to the next frame */ +skip_this_frame: + bp += (length + 3) & ~3; + if (bp >= lp->end_dma_buff) bp -= lp->dmasize*1024; + lp->rx_dma_ptr = bp; + return; + } + skb_reserve(skb, 2); /* longword align L3 header */ + skb->dev = dev; + + if (bp + length > lp->end_dma_buff) { + int semi_cnt = lp->end_dma_buff - bp; + memcpy(skb_put(skb,semi_cnt), bp, semi_cnt); + memcpy(skb_put(skb,length - semi_cnt), lp->dma_buff, + length - semi_cnt); + } else { + memcpy(skb_put(skb,length), bp, length); + } + bp += (length + 3) & ~3; + if (bp >= lp->end_dma_buff) bp -= lp->dmasize*1024; + lp->rx_dma_ptr = bp; + + if (net_debug > 3) { + printk( "%s: received %d byte DMA packet of type %x\n", + dev->name, length, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); + } + skb->protocol=eth_type_trans(skb,dev); + netif_rx(skb); + dev->last_rx = jiffies; + lp->stats.rx_packets++; + lp->stats.rx_bytes += length; +} + +#endif /* ALLOW_DMA */ + +void __init reset_chip(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + int ioaddr = dev->base_addr; + int reset_start_time; + + writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); + + /* wait 30 ms */ + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(30*HZ/1000); + + if (lp->chip_type != CS8900) { + /* Hardware problem requires PNP registers to be reconfigured after a reset */ + outw(PP_CS8920_ISAINT, ioaddr + ADD_PORT); + outb(dev->irq, ioaddr + DATA_PORT); + outb(0, ioaddr + DATA_PORT + 1); + + outw(PP_CS8920_ISAMemB, ioaddr + ADD_PORT); + outb((dev->mem_start >> 16) & 0xff, ioaddr + DATA_PORT); + outb((dev->mem_start >> 8) & 0xff, ioaddr + DATA_PORT + 1); + } + /* Wait until the chip is reset */ + reset_start_time = jiffies; + while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2) + ; +} + + +static void +control_dc_dc(struct net_device *dev, int on_not_off) +{ + struct net_local *lp = (struct net_local *)dev->priv; + unsigned int selfcontrol; + int timenow = jiffies; + /* control the DC to DC convertor in the SelfControl register. + Note: This is hooked up to a general purpose pin, might not + always be a DC to DC convertor. */ + + selfcontrol = HCB1_ENBL; /* Enable the HCB1 bit as an output */ + if (((lp->adapter_cnf & A_CNF_DC_DC_POLARITY) != 0) ^ on_not_off) + selfcontrol |= HCB1; + else + selfcontrol &= ~HCB1; + writereg(dev, PP_SelfCTL, selfcontrol); + + /* Wait for the DC/DC converter to power up - 500ms */ + while (jiffies - timenow < HZ) + ; +} + +#define DETECTED_NONE 0 +#define DETECTED_RJ45H 1 +#define DETECTED_RJ45F 2 +#define DETECTED_AUI 3 +#define DETECTED_BNC 4 + +static int +detect_tp(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + int timenow = jiffies; + int fdx; + + if (net_debug > 1) printk("%s: Attempting TP\n", dev->name); + + /* If connected to another full duplex capable 10-Base-T card the link pulses + seem to be lost when the auto detect bit in the LineCTL is set. + To overcome this the auto detect bit will be cleared whilst testing the + 10-Base-T interface. This would not be necessary for the sparrow chip but + is simpler to do it anyway. */ + writereg(dev, PP_LineCTL, lp->linectl &~ AUI_ONLY); + control_dc_dc(dev, 0); + + /* Delay for the hardware to work out if the TP cable is present - 150ms */ + for (timenow = jiffies; jiffies - timenow < 15; ) + ; + if ((readreg(dev, PP_LineST) & LINK_OK) == 0) + return DETECTED_NONE; + + if (lp->chip_type == CS8900) { + switch (lp->force & 0xf0) { +#if 0 + case FORCE_AUTO: + printk("%s: cs8900 doesn't autonegotiate\n",dev->name); + return DETECTED_NONE; +#endif + /* CS8900 doesn't support AUTO, change to HALF*/ + case FORCE_AUTO: + lp->force &= ~FORCE_AUTO; + lp->force |= FORCE_HALF; + break; + case FORCE_HALF: + break; + case FORCE_FULL: + writereg(dev, PP_TestCTL, readreg(dev, PP_TestCTL) | FDX_8900); + break; + } + fdx = readreg(dev, PP_TestCTL) & FDX_8900; + } else { + switch (lp->force & 0xf0) { + case FORCE_AUTO: + lp->auto_neg_cnf = AUTO_NEG_ENABLE; + break; + case FORCE_HALF: + lp->auto_neg_cnf = 0; + break; + case FORCE_FULL: + lp->auto_neg_cnf = RE_NEG_NOW | ALLOW_FDX; + break; + } + + writereg(dev, PP_AutoNegCTL, lp->auto_neg_cnf & AUTO_NEG_MASK); + + if ((lp->auto_neg_cnf & AUTO_NEG_BITS) == AUTO_NEG_ENABLE) { + printk(KERN_INFO "%s: negotiating duplex...\n",dev->name); + while (readreg(dev, PP_AutoNegST) & AUTO_NEG_BUSY) { + if (jiffies - timenow > 4000) { + printk(KERN_ERR "**** Full / half duplex auto-negotiation timed out ****\n"); + break; + } + } + } + fdx = readreg(dev, PP_AutoNegST) & FDX_ACTIVE; + } + if (fdx) + return DETECTED_RJ45F; + else + return DETECTED_RJ45H; +} + +/* send a test packet - return true if carrier bits are ok */ +static int +send_test_pkt(struct net_device *dev) +{ + char test_packet[] = { 0,0,0,0,0,0, 0,0,0,0,0,0, + 0, 46, /* A 46 in network order */ + 0, 0, /* DSAP=0 & SSAP=0 fields */ + 0xf3, 0 /* Control (Test Req + P bit set) */ }; + long timenow = jiffies; + + writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_TX_ON); + + memcpy(test_packet, dev->dev_addr, ETH_ALEN); + memcpy(test_packet+ETH_ALEN, dev->dev_addr, ETH_ALEN); + + writeword(dev, TX_CMD_PORT, TX_AFTER_ALL); + writeword(dev, TX_LEN_PORT, ETH_ZLEN); + + /* Test to see if the chip has allocated memory for the packet */ + while (jiffies - timenow < 5) + if (readreg(dev, PP_BusST) & READY_FOR_TX_NOW) + break; + if (jiffies - timenow >= 5) + return 0; /* this shouldn't happen */ + + /* Write the contents of the packet */ + outsw(dev->base_addr + TX_FRAME_PORT,test_packet,(ETH_ZLEN+1) >>1); + + if (net_debug > 1) printk("Sending test packet "); + /* wait a couple of jiffies for packet to be received */ + for (timenow = jiffies; jiffies - timenow < 3; ) + ; + if ((readreg(dev, PP_TxEvent) & TX_SEND_OK_BITS) == TX_OK) { + if (net_debug > 1) printk("succeeded\n"); + return 1; + } + if (net_debug > 1) printk("failed\n"); + return 0; +} + + +static int +detect_aui(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + + if (net_debug > 1) printk("%s: Attempting AUI\n", dev->name); + control_dc_dc(dev, 0); + + writereg(dev, PP_LineCTL, (lp->linectl &~ AUTO_AUI_10BASET) | AUI_ONLY); + + if (send_test_pkt(dev)) + return DETECTED_AUI; + else + return DETECTED_NONE; +} + +static int +detect_bnc(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + + if (net_debug > 1) printk("%s: Attempting BNC\n", dev->name); + control_dc_dc(dev, 1); + + writereg(dev, PP_LineCTL, (lp->linectl &~ AUTO_AUI_10BASET) | AUI_ONLY); + + if (send_test_pkt(dev)) + return DETECTED_BNC; + else + return DETECTED_NONE; +} + + +static void +write_irq(struct net_device *dev, int chip_type, int irq) +{ + int i; + + if (chip_type == CS8900) { + /* Search the mapping table for the corresponding IRQ pin. */ + for (i = 0; i != sizeof(cs8900_irq_map)/sizeof(cs8900_irq_map[0]); i++) + if (cs8900_irq_map[i] == irq) + break; + /* Not found */ + if (i == sizeof(cs8900_irq_map)/sizeof(cs8900_irq_map[0])) + i = 3; + writereg(dev, PP_CS8900_ISAINT, i); + } else { + writereg(dev, PP_CS8920_ISAINT, irq); + } +} + +/* Open/initialize the board. This is called (in the current kernel) + sometime after booting when the 'ifconfig' program is run. + + This routine should set everything up anew at each open, even + registers that "should" only need to be set once at boot, so that + there is non-reboot way to recover if something goes wrong. + */ + +/* AKPM: do we need to do any locking here? */ + +static int +net_open(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + int result = 0; + int i; + int ret; + +#ifndef CONFIG_SH_HICOSH4 /* uses irq#1, so this wont work */ + if (dev->irq < 2) { + /* Allow interrupts to be generated by the chip */ +/* Cirrus' release had this: */ +#if 0 + writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL)|ENABLE_IRQ ); +#endif +/* And 2.3.47 had this: */ + writereg(dev, PP_BusCTL, ENABLE_IRQ | MEMORY_ON); + + for (i = 2; i < CS8920_NO_INTS; i++) { + if ((1 << i) & lp->irq_map) { + if (request_irq(i, net_interrupt, 0, dev->name, dev) == 0) { + dev->irq = i; + write_irq(dev, lp->chip_type, i); + /* writereg(dev, PP_BufCFG, GENERATE_SW_INTERRUPT); */ + break; + } + } + } + + if (i >= CS8920_NO_INTS) { + writereg(dev, PP_BusCTL, 0); /* disable interrupts. */ + printk(KERN_ERR "cs89x0: can't get an interrupt\n"); + ret = -EAGAIN; + goto bad_out; + } + } + else +#endif + { + if (((1 << dev->irq) & lp->irq_map) == 0) { + printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n", + dev->name, dev->irq, lp->irq_map); + ret = -EAGAIN; + goto bad_out; + } +/* FIXME: Cirrus' release had this: */ + writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL)|ENABLE_IRQ ); +/* And 2.3.47 had this: */ +#if 0 + writereg(dev, PP_BusCTL, ENABLE_IRQ | MEMORY_ON); +#endif + write_irq(dev, lp->chip_type, dev->irq); + ret = request_irq(dev->irq, &net_interrupt, 0, dev->name, dev); + if (ret) { + if (net_debug) + printk(KERN_DEBUG "cs89x0: request_irq(%d) failed\n", dev->irq); + goto bad_out; + } + } + +#if ALLOW_DMA + if (lp->use_dma) { + if (lp->isa_config & ANY_ISA_DMA) { + unsigned long flags; + lp->dma_buff = (unsigned char *)__get_dma_pages(GFP_KERNEL, + get_order(lp->dmasize * 1024)); + + if (!lp->dma_buff) { + printk(KERN_ERR "%s: cannot get %dK memory for DMA\n", dev->name, lp->dmasize); + goto release_irq; + } + if (net_debug > 1) { + printk( "%s: dma %lx %lx\n", + dev->name, + (unsigned long)lp->dma_buff, + (unsigned long)virt_to_bus(lp->dma_buff)); + } + if ((unsigned long) lp->dma_buff >= MAX_DMA_ADDRESS || + !dma_page_eq(lp->dma_buff, lp->dma_buff+lp->dmasize*1024-1)) { + printk(KERN_ERR "%s: not usable as DMA buffer\n", dev->name); + goto release_irq; + } + memset(lp->dma_buff, 0, lp->dmasize * 1024); /* Why? */ + if (request_dma(dev->dma, dev->name)) { + printk(KERN_ERR "%s: cannot get dma channel %d\n", dev->name, dev->dma); + goto release_irq; + } + write_dma(dev, lp->chip_type, dev->dma); + lp->rx_dma_ptr = lp->dma_buff; + lp->end_dma_buff = lp->dma_buff + lp->dmasize*1024; + spin_lock_irqsave(&lp->lock, flags); + disable_dma(dev->dma); + clear_dma_ff(dev->dma); + set_dma_mode(dev->dma, 0x14); /* auto_init as well */ + set_dma_addr(dev->dma, virt_to_bus(lp->dma_buff)); + set_dma_count(dev->dma, lp->dmasize*1024); + enable_dma(dev->dma); + spin_unlock_irqrestore(&lp->lock, flags); + } + } +#endif /* ALLOW_DMA */ + + /* set the Ethernet address */ + for (i=0; i < ETH_ALEN/2; i++) + writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); + + /* while we're testing the interface, leave interrupts disabled */ + writereg(dev, PP_BusCTL, MEMORY_ON); + + /* Set the LineCTL quintuplet based on adapter configuration read from EEPROM */ + if ((lp->adapter_cnf & A_CNF_EXTND_10B_2) && (lp->adapter_cnf & A_CNF_LOW_RX_SQUELCH)) + lp->linectl = LOW_RX_SQUELCH; + else + lp->linectl = 0; + + /* check to make sure that they have the "right" hardware available */ + switch(lp->adapter_cnf & A_CNF_MEDIA_TYPE) { + case A_CNF_MEDIA_10B_T: result = lp->adapter_cnf & A_CNF_10B_T; break; + case A_CNF_MEDIA_AUI: result = lp->adapter_cnf & A_CNF_AUI; break; + case A_CNF_MEDIA_10B_2: result = lp->adapter_cnf & A_CNF_10B_2; break; + default: result = lp->adapter_cnf & (A_CNF_10B_T | A_CNF_AUI | A_CNF_10B_2); + } + if (!result) { + printk(KERN_ERR "%s: EEPROM is configured for unavailable media\n", dev->name); + release_irq: +#if ALLOW_DMA + release_dma_buff(lp); +#endif + writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) & ~(SERIAL_TX_ON | SERIAL_RX_ON)); + free_irq(dev->irq, dev); + ret = -EAGAIN; + goto bad_out; + } + + /* set the hardware to the configured choice */ + switch(lp->adapter_cnf & A_CNF_MEDIA_TYPE) { + case A_CNF_MEDIA_10B_T: + result = detect_tp(dev); + if (result==DETECTED_NONE) { + printk(KERN_WARNING "%s: 10Base-T (RJ-45) has no cable\n", dev->name); + if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ + result = DETECTED_RJ45H; /* Yes! I don't care if I see a link pulse */ + } + break; + case A_CNF_MEDIA_AUI: + result = detect_aui(dev); + if (result==DETECTED_NONE) { + printk(KERN_WARNING "%s: 10Base-5 (AUI) has no cable\n", dev->name); + if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ + result = DETECTED_AUI; /* Yes! I don't care if I see a carrrier */ + } + break; + case A_CNF_MEDIA_10B_2: + result = detect_bnc(dev); + if (result==DETECTED_NONE) { + printk(KERN_WARNING "%s: 10Base-2 (BNC) has no cable\n", dev->name); + if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ + result = DETECTED_BNC; /* Yes! I don't care if I can xmit a packet */ + } + break; + case A_CNF_MEDIA_AUTO: + writereg(dev, PP_LineCTL, lp->linectl | AUTO_AUI_10BASET); + if (lp->adapter_cnf & A_CNF_10B_T) + if ((result = detect_tp(dev)) != DETECTED_NONE) + break; + if (lp->adapter_cnf & A_CNF_AUI) + if ((result = detect_aui(dev)) != DETECTED_NONE) + break; + if (lp->adapter_cnf & A_CNF_10B_2) + if ((result = detect_bnc(dev)) != DETECTED_NONE) + break; + printk(KERN_ERR "%s: no media detected\n", dev->name); + goto release_irq; + } + switch(result) { + case DETECTED_NONE: + printk(KERN_ERR "%s: no network cable attached to configured media\n", dev->name); + goto release_irq; + case DETECTED_RJ45H: + printk(KERN_INFO "%s: using half-duplex 10Base-T (RJ-45)\n", dev->name); + break; + case DETECTED_RJ45F: + printk(KERN_INFO "%s: using full-duplex 10Base-T (RJ-45)\n", dev->name); + break; + case DETECTED_AUI: + printk(KERN_INFO "%s: using 10Base-5 (AUI)\n", dev->name); + break; + case DETECTED_BNC: + printk(KERN_INFO "%s: using 10Base-2 (BNC)\n", dev->name); + break; + } + + /* Turn on both receive and transmit operations */ + writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); + + /* Receive only error free packets addressed to this card */ + lp->rx_mode = 0; + writereg(dev, PP_RxCTL, DEF_RX_ACCEPT); + + lp->curr_rx_cfg = RX_OK_ENBL | RX_CRC_ERROR_ENBL; + + if (lp->isa_config & STREAM_TRANSFER) + lp->curr_rx_cfg |= RX_STREAM_ENBL; +#if ALLOW_DMA + set_dma_cfg(dev); +#endif + writereg(dev, PP_RxCFG, lp->curr_rx_cfg); + + writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL | + TX_LATE_COL_ENBL | TX_JBR_ENBL | TX_ANY_COL_ENBL | TX_16_COL_ENBL); + + writereg(dev, PP_BufCFG, READY_FOR_TX_ENBL | RX_MISS_COUNT_OVRFLOW_ENBL | +#if ALLOW_DMA + dma_bufcfg(dev) | +#endif + TX_COL_COUNT_OVRFLOW_ENBL | TX_UNDERRUN_ENBL); + + /* now that we've got our act together, enable everything */ + writereg(dev, PP_BusCTL, ENABLE_IRQ + | (dev->mem_start?MEMORY_ON : 0) /* turn memory on */ +#if ALLOW_DMA + | dma_busctl(dev) +#endif + ); + netif_start_queue(dev); + if (net_debug > 1) + printk("cs89x0: net_open() succeeded\n"); + return 0; +bad_out: + return ret; +} + +static void net_timeout(struct net_device *dev) +{ + /* If we get here, some higher level has decided we are broken. + There should really be a "kick me" function call instead. */ + if (net_debug > 0) printk("%s: transmit timed out, %s?\n", dev->name, + tx_done(dev) ? "IRQ conflict ?" : "network cable problem"); + /* Try to restart the adaptor. */ + netif_wake_queue(dev); +} + +static int net_send_packet(struct sk_buff *skb, struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + + if (net_debug > 3) { + printk("%s: sent %d byte packet of type %x\n", + dev->name, skb->len, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); + } + + /* keep the upload from being interrupted, since we + ask the chip to start transmitting before the + whole packet has been completely uploaded. */ + + spin_lock_irq(&lp->lock); + netif_stop_queue(dev); + + /* initiate a transmit sequence */ + writeword(dev, TX_CMD_PORT, lp->send_cmd); + writeword(dev, TX_LEN_PORT, skb->len); + + /* Test to see if the chip has allocated memory for the packet */ + if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) { + /* + * Gasp! It hasn't. But that shouldn't happen since + * we're waiting for TxOk, so return 1 and requeue this packet. + */ + + spin_unlock_irq(&lp->lock); + if (net_debug) printk("cs89x0: Tx buffer not free!\n"); + return 1; + } + /* Write the contents of the packet */ + outsw(dev->base_addr + TX_FRAME_PORT,skb->data,(skb->len+1) >>1); + spin_unlock_irq(&lp->lock); + dev->trans_start = jiffies; + dev_kfree_skb (skb); + + /* + * We DO NOT call netif_wake_queue() here. + * We also DO NOT call netif_start_queue(). + * + * Either of these would cause another bottom half run through + * net_send_packet() before this packet has fully gone out. That causes + * us to hit the "Gasp!" above and the send is rescheduled. it runs like + * a dog. We just return and wait for the Tx completion interrupt handler + * to restart the netdevice layer + */ + + return 0; +} + +/* The typical workload of the driver: + Handle the network interface interrupts. */ + +static void net_interrupt(int irq, void *dev_id, struct pt_regs * regs) +{ + struct net_device *dev = dev_id; + struct net_local *lp; + int ioaddr, status; + + ioaddr = dev->base_addr; + lp = (struct net_local *)dev->priv; + + /* we MUST read all the events out of the ISQ, otherwise we'll never + get interrupted again. As a consequence, we can't have any limit + on the number of times we loop in the interrupt handler. The + hardware guarantees that eventually we'll run out of events. Of + course, if you're on a slow machine, and packets are arriving + faster than you can read them off, you're screwed. Hasta la + vista, baby! */ + while ((status = readword(dev, ISQ_PORT))) { + if (net_debug > 4)printk("%s: event=%04x\n", dev->name, status); + switch(status & ISQ_EVENT_MASK) { + case ISQ_RECEIVER_EVENT: + /* Got a packet(s). */ + net_rx(dev); + break; + case ISQ_TRANSMITTER_EVENT: + lp->stats.tx_packets++; + netif_wake_queue(dev); /* Inform upper layers. */ + if ((status & ( TX_OK | + TX_LOST_CRS | + TX_SQE_ERROR | + TX_LATE_COL | + TX_16_COL)) != TX_OK) { + if ((status & TX_OK) == 0) lp->stats.tx_errors++; + if (status & TX_LOST_CRS) lp->stats.tx_carrier_errors++; + if (status & TX_SQE_ERROR) lp->stats.tx_heartbeat_errors++; + if (status & TX_LATE_COL) lp->stats.tx_window_errors++; + if (status & TX_16_COL) lp->stats.tx_aborted_errors++; + } + break; + case ISQ_BUFFER_EVENT: + if (status & READY_FOR_TX) { + /* we tried to transmit a packet earlier, + but inexplicably ran out of buffers. + That shouldn't happen since we only ever + load one packet. Shrug. Do the right + thing anyway. */ + netif_wake_queue(dev); /* Inform upper layers. */ + } + if (status & TX_UNDERRUN) { + if (net_debug > 0) printk("%s: transmit underrun\n", dev->name); + lp->send_underrun++; + if (lp->send_underrun == 3) lp->send_cmd = TX_AFTER_381; + else if (lp->send_underrun == 6) lp->send_cmd = TX_AFTER_ALL; + /* transmit cycle is done, although + frame wasn't transmitted - this + avoids having to wait for the upper + layers to timeout on us, in the + event of a tx underrun */ + netif_wake_queue(dev); /* Inform upper layers. */ + } +#if ALLOW_DMA + if (lp->use_dma && (status & RX_DMA)) { + int count = readreg(dev, PP_DmaFrameCnt); + while(count) { + if (net_debug > 5) + printk("%s: receiving %d DMA frames\n", dev->name, count); + if (net_debug > 2 && count >1) + printk("%s: receiving %d DMA frames\n", dev->name, count); + dma_rx(dev); + if (--count == 0) + count = readreg(dev, PP_DmaFrameCnt); + if (net_debug > 2 && count > 0) + printk("%s: continuing with %d DMA frames\n", dev->name, count); + } + } +#endif + break; + case ISQ_RX_MISS_EVENT: + lp->stats.rx_missed_errors += (status >>6); + break; + case ISQ_TX_COL_EVENT: + lp->stats.collisions += (status >>6); + break; + } + } +} + +static void +count_rx_errors(int status, struct net_local *lp) +{ + lp->stats.rx_errors++; + if (status & RX_RUNT) lp->stats.rx_length_errors++; + if (status & RX_EXTRA_DATA) lp->stats.rx_length_errors++; + if (status & RX_CRC_ERROR) if (!(status & (RX_EXTRA_DATA|RX_RUNT))) + /* per str 172 */ + lp->stats.rx_crc_errors++; + if (status & RX_DRIBBLE) lp->stats.rx_frame_errors++; + return; +} + +/* We have a good packet(s), get it/them out of the buffers. */ +static void +net_rx(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + struct sk_buff *skb; + int status, length; + + int ioaddr = dev->base_addr; + status = inw(ioaddr + RX_FRAME_PORT); + length = inw(ioaddr + RX_FRAME_PORT); + + if ((status & RX_OK) == 0) { + count_rx_errors(status, lp); + return; + } + + /* Malloc up new buffer. */ + skb = dev_alloc_skb(length + 2); + if (skb == NULL) { +#if 0 /* Again, this seems a cruel thing to do */ + printk(KERN_WARNING "%s: Memory squeeze, dropping packet.\n", dev->name); +#endif + lp->stats.rx_dropped++; + return; + } + skb_reserve(skb, 2); /* longword align L3 header */ + skb->dev = dev; + + insw(ioaddr + RX_FRAME_PORT, skb_put(skb, length), length >> 1); + if (length & 1) + skb->data[length-1] = inw(ioaddr + RX_FRAME_PORT); + + if (net_debug > 3) { + printk( "%s: received %d byte packet of type %x\n", + dev->name, length, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); + } + + skb->protocol=eth_type_trans(skb,dev); + netif_rx(skb); + dev->last_rx = jiffies; + lp->stats.rx_packets++; + lp->stats.rx_bytes += length; +} + +#if ALLOW_DMA +static void release_dma_buff(struct net_local *lp) +{ + if (lp->dma_buff) { + free_pages((unsigned long)(lp->dma_buff), get_order(lp->dmasize * 1024)); + lp->dma_buff = 0; + } +} +#endif + +/* The inverse routine to net_open(). */ +static int +net_close(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + + netif_stop_queue(dev); + + writereg(dev, PP_RxCFG, 0); + writereg(dev, PP_TxCFG, 0); + writereg(dev, PP_BufCFG, 0); + writereg(dev, PP_BusCTL, 0); + + free_irq(dev->irq, dev); + +#if ALLOW_DMA + if (lp->use_dma && lp->dma) { + free_dma(dev->dma); + release_dma_buff(lp); + } +#endif + + /* Update the statistics here. */ + return 0; +} + +/* Get the current statistics. This may be called with the card open or + closed. */ +static struct net_device_stats * +net_get_stats(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + unsigned long flags; + + spin_lock_irqsave(&lp->lock, flags); + /* Update the statistics from the device registers. */ + lp->stats.rx_missed_errors += (readreg(dev, PP_RxMiss) >> 6); + lp->stats.collisions += (readreg(dev, PP_TxCol) >> 6); + spin_unlock_irqrestore(&lp->lock, flags); + + return &lp->stats; +} + +static void set_multicast_list(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + unsigned long flags; + + spin_lock_irqsave(&lp->lock, flags); + if(dev->flags&IFF_PROMISC) + { + lp->rx_mode = RX_ALL_ACCEPT; + } + else if((dev->flags&IFF_ALLMULTI)||dev->mc_list) + { + /* The multicast-accept list is initialized to accept-all, and we + rely on higher-level filtering for now. */ + lp->rx_mode = RX_MULTCAST_ACCEPT; + } + else + lp->rx_mode = 0; + + writereg(dev, PP_RxCTL, DEF_RX_ACCEPT | lp->rx_mode); + + /* in promiscuous mode, we accept errored packets, so we have to enable interrupts on them also */ + writereg(dev, PP_RxCFG, lp->curr_rx_cfg | + (lp->rx_mode == RX_ALL_ACCEPT? (RX_CRC_ERROR_ENBL|RX_RUNT_ENBL|RX_EXTRA_DATA_ENBL) : 0)); + spin_unlock_irqrestore(&lp->lock, flags); +} + + +static int set_mac_address(struct net_device *dev, void *addr) +{ + int i; + + if (netif_running(dev)) + return -EBUSY; + if (net_debug) { + printk("%s: Setting MAC address to ", dev->name); + for (i = 0; i < 6; i++) + printk(" %2.2x", dev->dev_addr[i] = ((unsigned char *)addr)[i]); + printk(".\n"); + } + /* set the Ethernet address */ + for (i=0; i < ETH_ALEN/2; i++) + writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); + + return 0; +} + +#ifdef MODULE + +static struct net_device dev_cs89x0 = { + "", + 0, 0, 0, 0, + 0, 0, + 0, 0, 0, NULL, NULL }; + +/* + * Support the 'debug' module parm even if we're compiled for non-debug to + * avoid breaking someone's startup scripts + */ + +static int io; +static int irq; +static int debug; +static char media[8]; +static int duplex=-1; + +static int use_dma; /* These generate unused var warnings if ALLOW_DMA = 0 */ +static int dma; +static int dmasize=16; /* or 64 */ + +MODULE_PARM(io, "i"); +MODULE_PARM(irq, "i"); +MODULE_PARM(debug, "i"); +MODULE_PARM(media, "c8"); +MODULE_PARM(duplex, "i"); +MODULE_PARM(dma , "i"); +MODULE_PARM(dmasize , "i"); +MODULE_PARM(use_dma , "i"); +MODULE_PARM_DESC(io, "cs89x0 I/O base address"); +MODULE_PARM_DESC(irq, "cs89x0 IRQ number"); +#if DEBUGGING +MODULE_PARM_DESC(debug, "cs89x0 debug level (0-6)"); +#else +MODULE_PARM_DESC(debug, "(ignored)"); +#endif +MODULE_PARM_DESC(media, "Set cs89x0 adapter(s) media type(s) (rj45,bnc,aui)"); +/* No other value than -1 for duplex seems to be currently interpreted */ +MODULE_PARM_DESC(duplex, "(ignored)"); +#if ALLOW_DMA +MODULE_PARM_DESC(dma , "cs89x0 ISA DMA channel; ignored if use_dma=0"); +MODULE_PARM_DESC(dmasize , "cs89x0 DMA size in kB (16,64); ignored if use_dma=0"); +MODULE_PARM_DESC(use_dma , "cs89x0 using DMA (0-1)"); +#else +MODULE_PARM_DESC(dma , "(ignored)"); +MODULE_PARM_DESC(dmasize , "(ignored)"); +MODULE_PARM_DESC(use_dma , "(ignored)"); +#endif + +MODULE_AUTHOR("Mike Cruse, Russwll Nelson , Andrew Morton "); +MODULE_LICENSE("GPL"); + + +EXPORT_NO_SYMBOLS; + +/* +* media=t - specify media type + or media=2 + or media=aui + or medai=auto +* duplex=0 - specify forced half/full/autonegotiate duplex +* debug=# - debug level + + +* Default Chip Configuration: + * DMA Burst = enabled + * IOCHRDY Enabled = enabled + * UseSA = enabled + * CS8900 defaults to half-duplex if not specified on command-line + * CS8920 defaults to autoneg if not specified on command-line + * Use reset defaults for other config parameters + +* Assumptions: + * media type specified is supported (circuitry is present) + * if memory address is > 1MB, then required mem decode hw is present + * if 10B-2, then agent other than driver will enable DC/DC converter + (hw or software util) + + +*/ + +int +init_module(void) +{ + struct net_local *lp; + int ret = 0; + +#if DEBUGGING + net_debug = debug; +#else + debug = 0; +#endif + + dev_cs89x0.irq = irq; + dev_cs89x0.base_addr = io; + + dev_cs89x0.init = cs89x0_probe; + dev_cs89x0.priv = kmalloc(sizeof(struct net_local), GFP_KERNEL); + if (dev_cs89x0.priv == 0) { + printk(KERN_ERR "cs89x0.c: Out of memory.\n"); + return -ENOMEM; + } + memset(dev_cs89x0.priv, 0, sizeof(struct net_local)); + lp = (struct net_local *)dev_cs89x0.priv; + +#if ALLOW_DMA + if (use_dma) { + lp->use_dma = use_dma; + lp->dma = dma; + lp->dmasize = dmasize; + } +#endif + + spin_lock_init(&lp->lock); + + /* boy, they'd better get these right */ + if (!strcmp(media, "rj45")) + lp->adapter_cnf = A_CNF_MEDIA_10B_T | A_CNF_10B_T; + else if (!strcmp(media, "aui")) + lp->adapter_cnf = A_CNF_MEDIA_AUI | A_CNF_AUI; + else if (!strcmp(media, "bnc")) + lp->adapter_cnf = A_CNF_MEDIA_10B_2 | A_CNF_10B_2; + else + lp->adapter_cnf = A_CNF_MEDIA_10B_T | A_CNF_10B_T; + + if (duplex==-1) + lp->auto_neg_cnf = AUTO_NEG_ENABLE; + + if (io == 0) { + printk(KERN_ERR "cs89x0.c: Module autoprobing not allowed.\n"); + printk(KERN_ERR "cs89x0.c: Append io=0xNNN\n"); + ret = -EPERM; + goto out; + } + +#if ALLOW_DMA + if (use_dma && dmasize != 16 && dmasize != 64) { + printk(KERN_ERR "cs89x0.c: dma size must be either 16K or 64K, not %dK\n", dmasize); + ret = -EPERM; + goto out; + } +#endif + + if (register_netdev(&dev_cs89x0) != 0) { + printk(KERN_ERR "cs89x0.c: No card found at 0x%x\n", io); + ret = -ENXIO; + goto out; + } +out: + if (ret) + kfree(dev_cs89x0.priv); + return ret; +} + +void +cleanup_module(void) +{ + if (dev_cs89x0.priv != NULL) { + /* Free up the private structure, or leak memory :-) */ + unregister_netdev(&dev_cs89x0); + outw(PP_ChipID, dev_cs89x0.base_addr + ADD_PORT); + kfree(dev_cs89x0.priv); + dev_cs89x0.priv = NULL; /* gets re-allocated by cs89x0_probe1 */ + /* If we don't do this, we can't re-insmod it later. */ + release_region(dev_cs89x0.base_addr, NETCARD_IO_EXTENT); + } +} +#endif /* MODULE */ + +/* + * Local variables: + * version-control: t + * kept-new-versions: 5 + * c-indent-level: 8 + * tab-width: 8 + * End: + * + */ diff -x .svn -urN linux-2.6.8-rc2/drivers/net/cs89x0-old.h linux-2.6.8-rc2-pnp1/drivers/net/cs89x0-old.h --- linux-2.6.8-rc2/drivers/net/cs89x0-old.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/cs89x0-old.h 2004-07-27 14:01:31.000000000 +0200 @@ -0,0 +1,469 @@ +/* Copyright, 1988-1992, Russell Nelson, Crynwr Software + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, version 1. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ + /* offset 2h -> Model/Product Number */ + /* offset 3h -> Chip Revision Number */ + +#define PP_ISAIOB 0x0020 /* IO base address */ +#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ +#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ +#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ +#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ +#define PP_ISASOF 0x0026 /* ISA DMA offset */ +#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ +#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ +#define PP_CS8900_ISAMemB 0x002C /* Memory base */ +#define PP_CS8920_ISAMemB 0x0348 /* */ + +#define PP_ISABootBase 0x0030 /* Boot Prom base */ +#define PP_ISABootMask 0x0034 /* Boot Prom Mask */ + +/* EEPROM data and command registers */ +#define PP_EECMD 0x0040 /* NVR Interface Command register */ +#define PP_EEData 0x0042 /* NVR Interface Data Register */ +#define PP_DebugReg 0x0044 /* Debug Register */ + +#define PP_RxCFG 0x0102 /* Rx Bus config */ +#define PP_RxCTL 0x0104 /* Receive Control Register */ +#define PP_TxCFG 0x0106 /* Transmit Config Register */ +#define PP_TxCMD 0x0108 /* Transmit Command Register */ +#define PP_BufCFG 0x010A /* Bus configuration Register */ +#define PP_LineCTL 0x0112 /* Line Config Register */ +#define PP_SelfCTL 0x0114 /* Self Command Register */ +#define PP_BusCTL 0x0116 /* ISA bus control Register */ +#define PP_TestCTL 0x0118 /* Test Register */ +#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ + +#define PP_ISQ 0x0120 /* Interrupt Status */ +#define PP_RxEvent 0x0124 /* Rx Event Register */ +#define PP_TxEvent 0x0128 /* Tx Event Register */ +#define PP_BufEvent 0x012C /* Bus Event Register */ +#define PP_RxMiss 0x0130 /* Receive Miss Count */ +#define PP_TxCol 0x0132 /* Transmit Collision Count */ +#define PP_LineST 0x0134 /* Line State Register */ +#define PP_SelfST 0x0136 /* Self State register */ +#define PP_BusST 0x0138 /* Bus Status */ +#define PP_TDR 0x013C /* Time Domain Reflectometry */ +#define PP_AutoNegST 0x013E /* Auto Neg Status */ +#define PP_TxCommand 0x0144 /* Tx Command */ +#define PP_TxLength 0x0146 /* Tx Length */ +#define PP_LAF 0x0150 /* Hash Table */ +#define PP_IA 0x0158 /* Physical Address Register */ + +#define PP_RxStatus 0x0400 /* Receive start of frame */ +#define PP_RxLength 0x0402 /* Receive Length of frame */ +#define PP_RxFrame 0x0404 /* Receive frame pointer */ +#define PP_TxFrame 0x0A00 /* Transmit frame pointer */ + +/* Primary I/O Base Address. If no I/O base is supplied by the user, then this */ +/* can be used as the default I/O base to access the PacketPage Area. */ +#define DEFAULTIOBASE 0x0300 +#define FIRST_IO 0x020C /* First I/O port to check */ +#define LAST_IO 0x037C /* Last I/O port to check (+10h) */ +#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ +#define ADD_SIG 0x3000 /* Expected ID signature */ + +/* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */ +#ifdef CONFIG_MAC +#define LCSLOTBASE 0xfee00000 +#define MMIOBASE 0x40000 +#endif + +#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ + +#ifdef IBMEIPKT +#define EISA_ID_SIG 0x4D24 /* IBM */ +#define PART_NO_SIG 0x1010 /* IBM */ +#define MONGOOSE_BIT 0x0000 /* IBM */ +#else +#define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */ +#define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */ +#define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */ +#endif + +#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ + +/* Mask to find out the types of registers */ +#define REG_TYPE_MASK 0x001F + +/* Eeprom Commands */ +#define ERSE_WR_ENBL 0x00F0 +#define ERSE_WR_DISABLE 0x0000 + +/* Defines Control/Config register quintuplet numbers */ +#define RX_BUF_CFG 0x0003 +#define RX_CONTROL 0x0005 +#define TX_CFG 0x0007 +#define TX_COMMAND 0x0009 +#define BUF_CFG 0x000B +#define LINE_CONTROL 0x0013 +#define SELF_CONTROL 0x0015 +#define BUS_CONTROL 0x0017 +#define TEST_CONTROL 0x0019 + +/* Defines Status/Count registers quintuplet numbers */ +#define RX_EVENT 0x0004 +#define TX_EVENT 0x0008 +#define BUF_EVENT 0x000C +#define RX_MISS_COUNT 0x0010 +#define TX_COL_COUNT 0x0012 +#define LINE_STATUS 0x0014 +#define SELF_STATUS 0x0016 +#define BUS_STATUS 0x0018 +#define TDR 0x001C + +/* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */ +#define SKIP_1 0x0040 +#define RX_STREAM_ENBL 0x0080 +#define RX_OK_ENBL 0x0100 +#define RX_DMA_ONLY 0x0200 +#define AUTO_RX_DMA 0x0400 +#define BUFFER_CRC 0x0800 +#define RX_CRC_ERROR_ENBL 0x1000 +#define RX_RUNT_ENBL 0x2000 +#define RX_EXTRA_DATA_ENBL 0x4000 + +/* PP_RxCTL - Receive Control bit definition - Read/write */ +#define RX_IA_HASH_ACCEPT 0x0040 +#define RX_PROM_ACCEPT 0x0080 +#define RX_OK_ACCEPT 0x0100 +#define RX_MULTCAST_ACCEPT 0x0200 +#define RX_IA_ACCEPT 0x0400 +#define RX_BROADCAST_ACCEPT 0x0800 +#define RX_BAD_CRC_ACCEPT 0x1000 +#define RX_RUNT_ACCEPT 0x2000 +#define RX_EXTRA_DATA_ACCEPT 0x4000 +#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT) +/* Default receive mode - individually addressed, broadcast, and error free */ +#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) + +/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */ +#define TX_LOST_CRS_ENBL 0x0040 +#define TX_SQE_ERROR_ENBL 0x0080 +#define TX_OK_ENBL 0x0100 +#define TX_LATE_COL_ENBL 0x0200 +#define TX_JBR_ENBL 0x0400 +#define TX_ANY_COL_ENBL 0x0800 +#define TX_16_COL_ENBL 0x8000 + +/* PP_TxCMD - Transmit Command bit definition - Read-only */ +#define TX_START_4_BYTES 0x0000 +#define TX_START_64_BYTES 0x0040 +#define TX_START_128_BYTES 0x0080 +#define TX_START_ALL_BYTES 0x00C0 +#define TX_FORCE 0x0100 +#define TX_ONE_COL 0x0200 +#define TX_TWO_PART_DEFF_DISABLE 0x0400 +#define TX_NO_CRC 0x1000 +#define TX_RUNT 0x2000 + +/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */ +#define GENERATE_SW_INTERRUPT 0x0040 +#define RX_DMA_ENBL 0x0080 +#define READY_FOR_TX_ENBL 0x0100 +#define TX_UNDERRUN_ENBL 0x0200 +#define RX_MISS_ENBL 0x0400 +#define RX_128_BYTE_ENBL 0x0800 +#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 +#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 +#define RX_DEST_MATCH_ENBL 0x8000 + +/* PP_LineCTL - Line Control bit definition - Read/write */ +#define SERIAL_RX_ON 0x0040 +#define SERIAL_TX_ON 0x0080 +#define AUI_ONLY 0x0100 +#define AUTO_AUI_10BASET 0x0200 +#define MODIFIED_BACKOFF 0x0800 +#define NO_AUTO_POLARITY 0x1000 +#define TWO_PART_DEFDIS 0x2000 +#define LOW_RX_SQUELCH 0x4000 + +/* PP_SelfCTL - Software Self Control bit definition - Read/write */ +#define POWER_ON_RESET 0x0040 +#define SW_STOP 0x0100 +#define SLEEP_ON 0x0200 +#define AUTO_WAKEUP 0x0400 +#define HCB0_ENBL 0x1000 +#define HCB1_ENBL 0x2000 +#define HCB0 0x4000 +#define HCB1 0x8000 + +/* PP_BusCTL - ISA Bus Control bit definition - Read/write */ +#define RESET_RX_DMA 0x0040 +#define MEMORY_ON 0x0400 +#define DMA_BURST_MODE 0x0800 +#define IO_CHANNEL_READY_ON 0x1000 +#define RX_DMA_SIZE_64K 0x2000 +#define ENABLE_IRQ 0x8000 + +/* PP_TestCTL - Test Control bit definition - Read/write */ +#define LINK_OFF 0x0080 +#define ENDEC_LOOPBACK 0x0200 +#define AUI_LOOPBACK 0x0400 +#define BACKOFF_OFF 0x0800 +#define FDX_8900 0x4000 +#define FAST_TEST 0x8000 + +/* PP_RxEvent - Receive Event Bit definition - Read-only */ +#define RX_IA_HASHED 0x0040 +#define RX_DRIBBLE 0x0080 +#define RX_OK 0x0100 +#define RX_HASHED 0x0200 +#define RX_IA 0x0400 +#define RX_BROADCAST 0x0800 +#define RX_CRC_ERROR 0x1000 +#define RX_RUNT 0x2000 +#define RX_EXTRA_DATA 0x4000 + +#define HASH_INDEX_MASK 0x0FC00 + +/* PP_TxEvent - Transmit Event Bit definition - Read-only */ +#define TX_LOST_CRS 0x0040 +#define TX_SQE_ERROR 0x0080 +#define TX_OK 0x0100 +#define TX_LATE_COL 0x0200 +#define TX_JBR 0x0400 +#define TX_16_COL 0x8000 +#define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS) +#define TX_COL_COUNT_MASK 0x7800 + +/* PP_BufEvent - Buffer Event Bit definition - Read-only */ +#define SW_INTERRUPT 0x0040 +#define RX_DMA 0x0080 +#define READY_FOR_TX 0x0100 +#define TX_UNDERRUN 0x0200 +#define RX_MISS 0x0400 +#define RX_128_BYTE 0x0800 +#define TX_COL_OVRFLW 0x1000 +#define RX_MISS_OVRFLW 0x2000 +#define RX_DEST_MATCH 0x8000 + +/* PP_LineST - Ethernet Line Status bit definition - Read-only */ +#define LINK_OK 0x0080 +#define AUI_ON 0x0100 +#define TENBASET_ON 0x0200 +#define POLARITY_OK 0x1000 +#define CRS_OK 0x4000 + +/* PP_SelfST - Chip Software Status bit definition */ +#define ACTIVE_33V 0x0040 +#define INIT_DONE 0x0080 +#define SI_BUSY 0x0100 +#define EEPROM_PRESENT 0x0200 +#define EEPROM_OK 0x0400 +#define EL_PRESENT 0x0800 +#define EE_SIZE_64 0x1000 + +/* PP_BusST - ISA Bus Status bit definition */ +#define TX_BID_ERROR 0x0080 +#define READY_FOR_TX_NOW 0x0100 + +/* PP_AutoNegCTL - Auto Negotiation Control bit definition */ +#define RE_NEG_NOW 0x0040 +#define ALLOW_FDX 0x0080 +#define AUTO_NEG_ENABLE 0x0100 +#define NLP_ENABLE 0x0200 +#define FORCE_FDX 0x8000 +#define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE) +#define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW) + +/* PP_AutoNegST - Auto Negotiation Status bit definition */ +#define AUTO_NEG_BUSY 0x0080 +#define FLP_LINK 0x0100 +#define FLP_LINK_GOOD 0x0800 +#define LINK_FAULT 0x1000 +#define HDX_ACTIVE 0x4000 +#define FDX_ACTIVE 0x8000 + +/* The following block defines the ISQ event types */ +#define ISQ_RECEIVER_EVENT 0x04 +#define ISQ_TRANSMITTER_EVENT 0x08 +#define ISQ_BUFFER_EVENT 0x0c +#define ISQ_RX_MISS_EVENT 0x10 +#define ISQ_TX_COL_EVENT 0x12 + +#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ +#define ISQ_HIST 16 /* small history buffer */ +#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ + +#define TXRXBUFSIZE 0x0600 +#define RXDMABUFSIZE 0x8000 +#define RXDMASIZE 0x4000 +#define TXRX_LENGTH_MASK 0x07FF + +/* rx options bits */ +#define RCV_WITH_RXON 1 /* Set SerRx ON */ +#define RCV_COUNTS 2 /* Use Framecnt1 */ +#define RCV_PONG 4 /* Pong respondent */ +#define RCV_DONG 8 /* Dong operation */ +#define RCV_POLLING 0x10 /* Poll RxEvent */ +#define RCV_ISQ 0x20 /* Use ISQ, int */ +#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ +#define RCV_DMA 0x200 /* Set RxDMA only */ +#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ +#define RCV_FIXED_DATA 0x800 /* Every frame same */ +#define RCV_IO 0x1000 /* Use ISA IO only */ +#define RCV_MEMORY 0x2000 /* Use ISA Memory */ + +#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ +#define PKT_START PP_TxFrame /* Start of packet RAM */ + +#define RX_FRAME_PORT 0x0000 +#define TX_FRAME_PORT RX_FRAME_PORT +#define TX_CMD_PORT 0x0004 +#define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */ +#define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */ +#define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */ +#define TX_LEN_PORT 0x0006 +#define ISQ_PORT 0x0008 +#define ADD_PORT 0x000A +#define DATA_PORT 0x000C + +#define EEPROM_WRITE_EN 0x00F0 +#define EEPROM_WRITE_DIS 0x0000 +#define EEPROM_WRITE_CMD 0x0100 +#define EEPROM_READ_CMD 0x0200 + +/* Receive Header */ +/* Description of header of each packet in receive area of memory */ +#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ +#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ +#define RBUF_LEN_LOW 2 /* Length of received data - low byte */ +#define RBUF_LEN_HI 3 /* Length of received data - high byte */ +#define RBUF_HEAD_LEN 4 /* Length of this header */ + +#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ +#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ + +/* for bios scan */ +/* */ +#ifdef CSDEBUG +/* use these values for debugging bios scan */ +#define BIOS_START_SEG 0x00000 +#define BIOS_OFFSET_INC 0x0010 +#else +#define BIOS_START_SEG 0x0c000 +#define BIOS_OFFSET_INC 0x0200 +#endif + +#define BIOS_LAST_OFFSET 0x0fc00 + +/* Byte offsets into the EEPROM configuration buffer */ +#define ISA_CNF_OFFSET 0x6 +#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */ +#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */ + + /* the assumption here is that the bits in the eeprom are generally */ + /* in the same position as those in the autonegctl register. */ + /* Of course the IMM bit is not in that register so it must be */ + /* masked out */ +#define EE_FORCE_FDX 0x8000 +#define EE_NLP_ENABLE 0x0200 +#define EE_AUTO_NEG_ENABLE 0x0100 +#define EE_ALLOW_FDX 0x0080 +#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX) + +#define IMM_BIT 0x0040 /* ignore missing media */ + +#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) +#define A_CNF_10B_T 0x0001 +#define A_CNF_AUI 0x0002 +#define A_CNF_10B_2 0x0004 +#define A_CNF_MEDIA_TYPE 0x0060 +#define A_CNF_MEDIA_AUTO 0x0000 +#define A_CNF_MEDIA_10B_T 0x0020 +#define A_CNF_MEDIA_AUI 0x0040 +#define A_CNF_MEDIA_10B_2 0x0060 +#define A_CNF_DC_DC_POLARITY 0x0080 +#define A_CNF_NO_AUTO_POLARITY 0x2000 +#define A_CNF_LOW_RX_SQUELCH 0x4000 +#define A_CNF_EXTND_10B_2 0x8000 + +#define PACKET_PAGE_OFFSET 0x8 + +/* Bit definitions for the ISA configuration word from the EEPROM */ +#define INT_NO_MASK 0x000F +#define DMA_NO_MASK 0x0070 +#define ISA_DMA_SIZE 0x0200 +#define ISA_AUTO_RxDMA 0x0400 +#define ISA_RxDMA 0x0800 +#define DMA_BURST 0x1000 +#define STREAM_TRANSFER 0x2000 +#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) + +/* DMA controller registers */ +#define DMA_BASE 0x00 /* DMA controller base */ +#define DMA_BASE_2 0x0C0 /* DMA controller base */ + +#define DMA_STAT 0x0D0 /* DMA controller status register */ +#define DMA_MASK 0x0D4 /* DMA controller mask register */ +#define DMA_MODE 0x0D6 /* DMA controller mode register */ +#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ + +/* DMA data */ +#define DMA_DISABLE 0x04 /* Disable channel n */ +#define DMA_ENABLE 0x00 /* Enable channel n */ +/* Demand transfers, incr. address, auto init, writes, ch. n */ +#define DMA_RX_MODE 0x14 +/* Demand transfers, incr. address, auto init, reads, ch. n */ +#define DMA_TX_MODE 0x18 + +#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ + +#define CS8900 0x0000 +#define CS8920 0x4000 +#define CS8920M 0x6000 +#define REVISON_BITS 0x1F00 +#define EEVER_NUMBER 0x12 +#define CHKSUM_LEN 0x14 +#define CHKSUM_VAL 0x0000 +#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ +#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ +#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ +#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ +#ifdef CONFIG_SH_HICOSH4 +#define CS8900_IRQ_MAP 0x0002 /* HiCO-SH4 board has its IRQ on #1 */ +#else +#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ +#endif + +#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ + +#define PNP_ADD_PORT 0x0279 +#define PNP_WRITE_PORT 0x0A79 + +#define GET_PNP_ISA_STRUCT 0x40 +#define PNP_ISA_STRUCT_LEN 0x06 +#define PNP_CSN_CNT_OFF 0x01 +#define PNP_RD_PORT_OFF 0x02 +#define PNP_FUNCTION_OK 0x00 +#define PNP_WAKE 0x03 +#define PNP_RSRC_DATA 0x04 +#define PNP_RSRC_READY 0x01 +#define PNP_STATUS 0x05 +#define PNP_ACTIVATE 0x30 +#define PNP_CNF_IO_H 0x60 +#define PNP_CNF_IO_L 0x61 +#define PNP_CNF_INT 0x70 +#define PNP_CNF_DMA 0x74 +#define PNP_CNF_MEM 0x48 + +#define BIT0 1 +#define BIT15 0x8000 + diff -x .svn -urN linux-2.6.8-rc2/drivers/net/Kconfig linux-2.6.8-rc2-pnp1/drivers/net/Kconfig --- linux-2.6.8-rc2/drivers/net/Kconfig 2004-07-27 14:08:05.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/net/Kconfig 2004-07-27 14:01:20.000000000 +0200 @@ -743,7 +743,7 @@ config NET_VENDOR_SMC bool "Western Digital/SMC cards" - depends on NET_ETHERNET && (ISA || MCA || EISA || MAC) + depends on NET_ETHERNET && (ISA || MCA || EISA || MAC || ARM) help If you have a network (Ethernet) card belonging to this class, say Y and read the Ethernet-HOWTO, available from @@ -814,10 +814,10 @@ will be called smc-ultra32. config SMC91X - tristate "SMC 91C9x/91C1xxx support" + tristate "SMC 91C9x/91C1xxx support (new 2.6.7-bk17 driver)" select CRC32 select MII - depends on NET_ETHERNET && (ARM || REDWOOD_5 || REDWOOD_6) + depends on NET_VENDOR_SMC && (ARM || REDWOOD_5 || REDWOOD_6) help This is a driver for SMC's 91x series of Ethernet chipsets, including the SMC91C94 and the SMC91C111. Say Y if you want it @@ -831,21 +831,29 @@ module, say M here and read as well as . -config SMC9194 - tristate "SMC 9194 support" - depends on NET_VENDOR_SMC && (ISA || MAC && BROKEN) +config SMC91X_OLD + tristate "SMC 91C9x/91C1xxx support (old driver)" + depends on NET_VENDOR_SMC select CRC32 - ---help--- - This is support for the SMC9xxx based Ethernet cards. Choose this - option if you have a DELL laptop with the docking station, or - another SMC9192/9194 based chipset. Say Y if you want it compiled - into the kernel, and read the file - and the Ethernet-HOWTO, - available from . + select MII + help + This is a driver for SMC's 91x series of Ethernet chipsets, + including the SMC91C94 and the SMC91C111. Say Y if you want it + compiled into the kernel, and read the file + and the Ethernet-HOWTO, + available from . - To compile this driver as a module, choose M here and read - . The module - will be called smc9194. +config SMC91X_OLD_TX_DMA + bool "Enable TX DMA" + depends on SMC91X_OLD + help + Enable Tx DMA transfer. + +config SMC91X_OLD_THROTTLE_TX + bool "Throttle TX packets" + depends on SMC91X_OLD + help + Throttle TX packets. config NET_VENDOR_RACAL bool "Racal-Interlan (Micom) NI cards" @@ -1365,6 +1373,18 @@ . The module will be called cs89x. +config CIRRUS + tristate "CS89x0 support (ARM driver)" + depends on ARM + ---help--- + Support for CS89x0 chipsets based Ethernet cards. If you have a + network (Ethernet) card of this type, say Y and read the + Ethernet-HOWTO, available from + as well as + . + + This is the ARM driver from 2.4. + config TC35815 tristate "TOSHIBA TC35815 Ethernet support" depends on NET_PCI && PCI && TOSHIBA_JMR3927 diff -x .svn -urN linux-2.6.8-rc2/drivers/net/Makefile linux-2.6.8-rc2-pnp1/drivers/net/Makefile --- linux-2.6.8-rc2/drivers/net/Makefile 2004-07-27 14:08:05.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/net/Makefile 2004-07-27 14:01:27.000000000 +0200 @@ -73,7 +73,6 @@ obj-$(CONFIG_SHAPER) += shaper.o obj-$(CONFIG_SK_G16) += sk_g16.o obj-$(CONFIG_HP100) += hp100.o -obj-$(CONFIG_SMC9194) += smc9194.o obj-$(CONFIG_FEC) += fec.o obj-$(CONFIG_68360_ENET) += 68360enet.o obj-$(CONFIG_ARM_ETHERH) += 8390.o @@ -94,6 +93,8 @@ obj-$(CONFIG_B44) += b44.o obj-$(CONFIG_FORCEDETH) += forcedeth.o obj-$(CONFIG_NE_H8300) += ne-h8300.o 8390.o +obj-$(CONFIG_SMC91X_OLD) += smc91x.o +obj-$(CONFIG_SMC91X) += smc91x.o obj-$(CONFIG_PPP) += ppp_generic.o slhc.o obj-$(CONFIG_PPP_ASYNC) += ppp_async.o @@ -166,6 +167,7 @@ obj-$(CONFIG_HYDRA) += hydra.o 8390.o obj-$(CONFIG_ARIADNE) += ariadne.o obj-$(CONFIG_CS89x0) += cs89x0.o +obj-$(CONFIG_CIRRUS) += cirrus.o obj-$(CONFIG_MACSONIC) += macsonic.o obj-$(CONFIG_MACMACE) += macmace.o obj-$(CONFIG_MAC89x0) += mac89x0.o diff -x .svn -urN linux-2.6.8-rc2/drivers/net/smc91x-bk16.c linux-2.6.8-rc2-pnp1/drivers/net/smc91x-bk16.c --- linux-2.6.8-rc2/drivers/net/smc91x-bk16.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/smc91x-bk16.c 2004-07-27 14:01:25.000000000 +0200 @@ -0,0 +1,2173 @@ +/* + * smc91x.c + * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. + * + * Copyright (C) 1996 by Erik Stahlman + * Copyright (C) 2001 Standard Microsystems Corporation + * Developed by Simple Network Magic Corporation + * Copyright (C) 2003 Monta Vista Software, Inc. + * Unified SMC91x driver by Nicolas Pitre + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Arguments: + * io = for the base address + * irq = for the IRQ + * nowait = 0 for normal wait states, 1 eliminates additional wait states + * + * original author: + * Erik Stahlman + * + * hardware multicast code: + * Peter Cammaert + * + * contributors: + * Daris A Nevil + * Nicolas Pitre + * Russell King + * + * History: + * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet + * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" + * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 + * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 + * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 + * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support + * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, + * more bus abstraction, big cleanup, etc. + * 29/09/03 Russell King - add driver model support + * - ethtool support + * - convert to use generic MII interface + * - add link up/down notification + * - don't try to handle full negotiation in + * smc_phy_configure + * - clean up (and fix stack overrun) in PHY + * MII read/write functions + */ +static const char version[] = + "smc91x.c: v1.0, mar 07 2003 by Nicolas Pitre \n"; + +/* Debugging level */ +#ifndef SMC_DEBUG +#define SMC_DEBUG 0 +#endif + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#ifdef CONFIG_ARM +#include +#endif +#include + +#include "smc91x.h" + +#ifdef CONFIG_ISA +/* + * the LAN91C111 can be at any of the following port addresses. To change, + * for a slightly different card, you can add it to the array. Keep in + * mind that the array must end in zero. + */ +static unsigned int smc_portlist[] __initdata = { + 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0, + 0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0, 0 +}; + +#ifndef SMC_IOADDR +# define SMC_IOADDR -1 +#endif +static unsigned long io = SMC_IOADDR; +module_param(io, ulong, 0400); +MODULE_PARM_DESC(io, "I/O base address"); + +#ifndef SMC_IRQ +# define SMC_IRQ -1 +#endif +static int irq = SMC_IRQ; +module_param(irq, int, 0400); +MODULE_PARM_DESC(irq, "IRQ number"); + +#endif /* CONFIG_ISA */ + +#ifndef SMC_NOWAIT +# define SMC_NOWAIT 0 +#endif +static int nowait = SMC_NOWAIT; +module_param(nowait, int, 0400); +MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); + +/* + * Transmit timeout, default 5 seconds. + */ +static int watchdog = 5000; +module_param(watchdog, int, 0400); +MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); + +MODULE_LICENSE("GPL"); + +/* + * The internal workings of the driver. If you are changing anything + * here with the SMC stuff, you should have the datasheet and know + * what you are doing. + */ +#define CARDNAME "smc91x" + +/* + * Use power-down feature of the chip + */ +#define POWER_DOWN 1 + +/* + * Wait time for memory to be free. This probably shouldn't be + * tuned that much, as waiting for this means nothing else happens + * in the system + */ +#define MEMORY_WAIT_TIME 16 + +/* + * This selects whether TX packets are sent one by one to the SMC91x internal + * memory and throttled until transmission completes. This may prevent + * RX overruns a litle by keeping much of the memory free for RX packets + * but to the expense of reduced TX throughput and increased IRQ overhead. + * Note this is not a cure for a too slow data bus or too high IRQ latency. + */ +#define THROTTLE_TX_PKTS 0 + +/* + * The MII clock high/low times. 2x this number gives the MII clock period + * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) + */ +#define MII_DELAY 1 + +/* store this information for the driver.. */ +struct smc_local { + /* + * If I have to wait until memory is available to send a + * packet, I will store the skbuff here, until I get the + * desired memory. Then, I'll send it out and free it. + */ + struct sk_buff *saved_skb; + + /* + * these are things that the kernel wants me to keep, so users + * can find out semi-useless statistics of how well the card is + * performing + */ + struct net_device_stats stats; + + /* version/revision of the SMC91x chip */ + int version; + + /* Contains the current active transmission mode */ + int tcr_cur_mode; + + /* Contains the current active receive mode */ + int rcr_cur_mode; + + /* Contains the current active receive/phy mode */ + int rpc_cur_mode; + int ctl_rfduplx; + int ctl_rspeed; + + u32 msg_enable; + u32 phy_type; + struct mii_if_info mii; + spinlock_t lock; + +#ifdef SMC_USE_PXA_DMA + /* DMA needs the physical address of the chip */ + u_long physaddr; +#endif +}; + +#if SMC_DEBUG > 0 +#define DBG(n, args...) \ + do { \ + if (SMC_DEBUG >= (n)) \ + printk(KERN_DEBUG args); \ + } while (0) + +#define PRINTK(args...) printk(args) +#else +#define DBG(n, args...) do { } while(0) +#define PRINTK(args...) printk(KERN_DEBUG args) +#endif + +#if SMC_DEBUG > 3 +static void PRINT_PKT(u_char *buf, int length) +{ + int i; + int remainder; + int lines; + + lines = length / 16; + remainder = length % 16; + + for (i = 0; i < lines ; i ++) { + int cur; + for (cur = 0; cur < 8; cur++) { + u_char a, b; + a = *buf++; + b = *buf++; + printk("%02x%02x ", a, b); + } + printk("\n"); + } + for (i = 0; i < remainder/2 ; i++) { + u_char a, b; + a = *buf++; + b = *buf++; + printk("%02x%02x ", a, b); + } + printk("\n"); +} +#else +#define PRINT_PKT(x...) do { } while(0) +#endif + + +/* this enables an interrupt in the interrupt mask register */ +#define SMC_ENABLE_INT(x) do { \ + unsigned long flags; \ + unsigned char mask; \ + spin_lock_irqsave(&lp->lock, flags); \ + mask = SMC_GET_INT_MASK(); \ + mask |= (x); \ + SMC_SET_INT_MASK(mask); \ + spin_unlock_irqrestore(&lp->lock, flags); \ +} while (0) + +/* this disables an interrupt from the interrupt mask register */ +#define SMC_DISABLE_INT(x) do { \ + unsigned long flags; \ + unsigned char mask; \ + spin_lock_irqsave(&lp->lock, flags); \ + mask = SMC_GET_INT_MASK(); \ + mask &= ~(x); \ + SMC_SET_INT_MASK(mask); \ + spin_unlock_irqrestore(&lp->lock, flags); \ +} while (0) + +/* + * Wait while MMU is busy. This is usually in the order of a few nanosecs + * if at all, but let's avoid deadlocking the system if the hardware + * decides to go south. + */ +#define SMC_WAIT_MMU_BUSY() do { \ + if (unlikely(SMC_GET_MMU_CMD() & MC_BUSY)) { \ + unsigned long timeout = jiffies + 2; \ + while (SMC_GET_MMU_CMD() & MC_BUSY) { \ + if (time_after(jiffies, timeout)) { \ + printk("%s: timeout %s line %d\n", \ + dev->name, __FILE__, __LINE__); \ + break; \ + } \ + cpu_relax(); \ + } \ + } \ +} while (0) + + +/* + * this does a soft reset on the device + */ +static void smc_reset(struct net_device *dev) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int ctl, cfg; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + /* + * This resets the registers mostly to defaults, but doesn't + * affect EEPROM. That seems unnecessary + */ + SMC_SELECT_BANK(0); + SMC_SET_RCR(RCR_SOFTRST); + + /* + * Setup the Configuration Register + * This is necessary because the CONFIG_REG is not affected + * by a soft reset + */ + SMC_SELECT_BANK(1); + + cfg = CONFIG_DEFAULT; + + /* + * Setup for fast accesses if requested. If the card/system + * can't handle it then there will be no recovery except for + * a hard reset or power cycle + */ + if (nowait) + cfg |= CONFIG_NO_WAIT; + + /* + * Release from possible power-down state + * Configuration register is not affected by Soft Reset + */ + cfg |= CONFIG_EPH_POWER_EN; + + SMC_SET_CONFIG(cfg); + + /* this should pause enough for the chip to be happy */ + /* + * elaborate? What does the chip _need_? --jgarzik + * + * This seems to be undocumented, but something the original + * driver(s) have always done. Suspect undocumented timing + * info/determined empirically. --rmk + */ + udelay(1); + + /* Disable transmit and receive functionality */ + SMC_SELECT_BANK(0); + SMC_SET_RCR(RCR_CLEAR); + SMC_SET_TCR(TCR_CLEAR); + + SMC_SELECT_BANK(1); + ctl = SMC_GET_CTL() | CTL_LE_ENABLE; + + /* + * Set the control register to automatically release successfully + * transmitted packets, to make the best use out of our limited + * memory + */ +#if ! THROTTLE_TX_PKTS + ctl |= CTL_AUTO_RELEASE; +#else + ctl &= ~CTL_AUTO_RELEASE; +#endif + SMC_SET_CTL(ctl); + + /* Disable all interrupts */ + SMC_SELECT_BANK(2); + SMC_SET_INT_MASK(0); + + /* Reset the MMU */ + SMC_SET_MMU_CMD(MC_RESET); + SMC_WAIT_MMU_BUSY(); +} + +/* + * Enable Interrupts, Receive, and Transmit + */ +static void smc_enable(struct net_device *dev) +{ + unsigned long ioaddr = dev->base_addr; + struct smc_local *lp = netdev_priv(dev); + int mask; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + /* see the header file for options in TCR/RCR DEFAULT */ + SMC_SELECT_BANK(0); + SMC_SET_TCR(lp->tcr_cur_mode); + SMC_SET_RCR(lp->rcr_cur_mode); + + /* now, enable interrupts */ + mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; + if (lp->version >= (CHIP_91100 << 4)) + mask |= IM_MDINT; + SMC_SELECT_BANK(2); + SMC_SET_INT_MASK(mask); +} + +/* + * this puts the device in an inactive state + */ +static void smc_shutdown(unsigned long ioaddr) +{ + DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__); + + /* no more interrupts for me */ + SMC_SELECT_BANK(2); + SMC_SET_INT_MASK(0); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK(0); + SMC_SET_RCR(RCR_CLEAR); + SMC_SET_TCR(TCR_CLEAR); + +#ifdef POWER_DOWN + /* finally, shut the chip down */ + SMC_SELECT_BANK(1); + SMC_SET_CONFIG(SMC_GET_CONFIG() & ~CONFIG_EPH_POWER_EN); +#endif +} + +/* + * This is the procedure to handle the receipt of a packet. + */ +static inline void smc_rcv(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + unsigned int packet_number, status, packet_len; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + packet_number = SMC_GET_RXFIFO(); + if (unlikely(packet_number & RXFIFO_REMPTY)) { + PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name); + return; + } + + /* read from start of packet */ + SMC_SET_PTR(PTR_READ | PTR_RCV | PTR_AUTOINC); + + /* First two words are status and packet length */ + SMC_GET_PKT_HDR(status, packet_len); + packet_len &= 0x07ff; /* mask off top bits */ + DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", + dev->name, packet_number, status, + packet_len, packet_len); + + if (unlikely(status & RS_ERRORS)) { + lp->stats.rx_errors++; + if (status & RS_ALGNERR) + lp->stats.rx_frame_errors++; + if (status & (RS_TOOSHORT | RS_TOOLONG)) + lp->stats.rx_length_errors++; + if (status & RS_BADCRC) + lp->stats.rx_crc_errors++; + } else { + struct sk_buff *skb; + unsigned char *data; + unsigned int data_len; + + /* set multicast stats */ + if (status & RS_MULTICAST) + lp->stats.multicast++; + + /* + * Actual payload is packet_len - 4 (or 3 if odd byte). + * We want skb_reserve(2) and the final ctrl word + * (2 bytes, possibly containing the payload odd byte). + * Ence packet_len - 4 + 2 + 2. + */ + skb = dev_alloc_skb(packet_len); + if (unlikely(skb == NULL)) { + printk(KERN_NOTICE "%s: Low memory, packet dropped.\n", + dev->name); + lp->stats.rx_dropped++; + goto done; + } + + /* Align IP header to 32 bits */ + skb_reserve(skb, 2); + + /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ + if (lp->version == 0x90) + status |= RS_ODDFRAME; + + /* + * If odd length: packet_len - 3, + * otherwise packet_len - 4. + */ + data_len = packet_len - ((status & RS_ODDFRAME) ? 3 : 4); + data = skb_put(skb, data_len); + SMC_PULL_DATA(data, packet_len - 2); + + PRINT_PKT(data, packet_len - 2); + + dev->last_rx = jiffies; + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + lp->stats.rx_packets++; + lp->stats.rx_bytes += data_len; + } + +done: + SMC_WAIT_MMU_BUSY(); + SMC_SET_MMU_CMD(MC_RELEASE); +} + +/* + * This is called to actually send a packet to the chip. + * Returns non-zero when successful. + */ +static void smc_hardware_send_packet(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + struct sk_buff *skb = lp->saved_skb; + unsigned int packet_no, len; + unsigned char *buf; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + packet_no = SMC_GET_AR(); + if (unlikely(packet_no & AR_FAILED)) { + printk("%s: Memory allocation failed.\n", dev->name); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_fifo_errors++; + dev_kfree_skb_any(skb); + return; + } + + /* point to the beginning of the packet */ + SMC_SET_PN(packet_no); + SMC_SET_PTR(PTR_AUTOINC); + + buf = skb->data; + len = skb->len; + DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", + dev->name, packet_no, len, len, buf); + PRINT_PKT(buf, len); + + /* + * Send the packet length (+6 for status words, length, and ctl. + * The card will pad to 64 bytes with zeroes if packet is too small. + */ + SMC_PUT_PKT_HDR(0, len + 6); + + /* send the actual data */ + SMC_PUSH_DATA(buf, len & ~1); + + /* Send final ctl word with the last byte if there is one */ + SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG); + + /* and let the chipset deal with it */ + SMC_SET_MMU_CMD(MC_ENQUEUE); + SMC_ACK_INT(IM_TX_EMPTY_INT); + + dev->trans_start = jiffies; + dev_kfree_skb_any(skb); + lp->saved_skb = NULL; + lp->stats.tx_packets++; + lp->stats.tx_bytes += len; +} + +/* + * Since I am not sure if I will have enough room in the chip's ram + * to store the packet, I call this routine which either sends it + * now, or set the card to generates an interrupt when ready + * for the packet. + */ +static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + unsigned int numPages, poll_count, status, saved_bank; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + BUG_ON(lp->saved_skb != NULL); + lp->saved_skb = skb; + + /* + * The MMU wants the number of pages to be the number of 256 bytes + * 'pages', minus 1 (since a packet can't ever have 0 pages :)) + * + * The 91C111 ignores the size bits, but earlier models don't. + * + * Pkt size for allocating is data length +6 (for additional status + * words, length and ctl) + * + * If odd size then last byte is included in ctl word. + */ + numPages = ((skb->len & ~1) + (6 - 1)) >> 8; + if (unlikely(numPages > 7)) { + printk("%s: Far too big packet error.\n", dev->name); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_dropped++; + dev_kfree_skb(skb); + return 0; + } + + /* now, try to allocate the memory */ + saved_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(2); + SMC_SET_MMU_CMD(MC_ALLOC | numPages); + + /* + * Poll the chip for a short amount of time in case the + * allocation succeeds quickly. + */ + poll_count = MEMORY_WAIT_TIME; + do { + status = SMC_GET_INT(); + if (status & IM_ALLOC_INT) { + SMC_ACK_INT(IM_ALLOC_INT); + break; + } + } while (--poll_count); + + if (!poll_count) { + /* oh well, wait until the chip finds memory later */ + netif_stop_queue(dev); + DBG(2, "%s: TX memory allocation deferred.\n", dev->name); + SMC_ENABLE_INT(IM_ALLOC_INT); + } else { + /* + * Allocation succeeded: push packet to the chip's own memory + * immediately. + * + * If THROTTLE_TX_PKTS is selected that means we don't want + * more than a single TX packet taking up space in the chip's + * internal memory at all time, in which case we stop the + * queue right here until we're notified of TX completion. + * + * Otherwise we're quite happy to feed more TX packets right + * away for better TX throughput, in which case the queue is + * left active. + */ +#if THROTTLE_TX_PKTS + netif_stop_queue(dev); +#endif + smc_hardware_send_packet(dev); + SMC_ENABLE_INT(IM_TX_INT | IM_TX_EMPTY_INT); + } + + SMC_SELECT_BANK(saved_bank); + return 0; +} + +/* + * This handles a TX interrupt, which is only called when: + * - a TX error occurred, or + * - CTL_AUTO_RELEASE is not set and TX of a packet completed. + */ +static void smc_tx(struct net_device *dev) +{ + unsigned long ioaddr = dev->base_addr; + struct smc_local *lp = netdev_priv(dev); + unsigned int saved_packet, packet_no, tx_status, pkt_len; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + /* If the TX FIFO is empty then nothing to do */ + packet_no = SMC_GET_TXFIFO(); + if (unlikely(packet_no & TXFIFO_TEMPTY)) { + PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name); + return; + } + + /* select packet to read from */ + saved_packet = SMC_GET_PN(); + SMC_SET_PN(packet_no); + + /* read the first word (status word) from this packet */ + SMC_SET_PTR(PTR_AUTOINC | PTR_READ); + SMC_GET_PKT_HDR(tx_status, pkt_len); + DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n", + dev->name, tx_status, packet_no); + + if (!(tx_status & TS_SUCCESS)) + lp->stats.tx_errors++; + if (tx_status & TS_LOSTCAR) + lp->stats.tx_carrier_errors++; + + SMC_WAIT_MMU_BUSY(); + + if (tx_status & TS_LATCOL) { + PRINTK("%s: late collision occurred on last xmit\n", dev->name); + lp->stats.tx_window_errors++; + /* It's really cheap to requeue the pkt here */ + SMC_SET_MMU_CMD( MC_ENQUEUE ); + } else { + /* kill the packet */ + SMC_SET_MMU_CMD(MC_FREEPKT); + } + + /* Don't restore Packet Number Reg until busy bit is cleared */ + SMC_WAIT_MMU_BUSY(); + SMC_SET_PN(saved_packet); + + /* re-enable transmit */ + SMC_SELECT_BANK(0); + SMC_SET_TCR(lp->tcr_cur_mode); + SMC_SELECT_BANK(2); +} + + +/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ + +static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int mii_reg, mask; + + mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO); + mii_reg |= MII_MDOE; + + for (mask = 1 << (bits - 1); mask; mask >>= 1) { + if (val & mask) + mii_reg |= MII_MDO; + else + mii_reg &= ~MII_MDO; + + SMC_SET_MII(mii_reg); + udelay(MII_DELAY); + SMC_SET_MII(mii_reg | MII_MCLK); + udelay(MII_DELAY); + } +} + +static unsigned int smc_mii_in(struct net_device *dev, int bits) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int mii_reg, mask, val; + + mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO); + SMC_SET_MII(mii_reg); + + for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { + if (SMC_GET_MII() & MII_MDI) + val |= mask; + + SMC_SET_MII(mii_reg); + udelay(MII_DELAY); + SMC_SET_MII(mii_reg | MII_MCLK); + udelay(MII_DELAY); + } + + return val; +} + +/* + * Reads a register from the MII Management serial interface + */ +static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int phydata, old_bank; + + /* Save the current bank, and select bank 3 */ + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(3); + + /* Idle - 32 ones */ + smc_mii_out(dev, 0xffffffff, 32); + + /* Start code (01) + read (10) + phyaddr + phyreg */ + smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); + + /* Turnaround (2bits) + phydata */ + phydata = smc_mii_in(dev, 18); + + /* Return to idle state */ + SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO)); + + /* And select original bank */ + SMC_SELECT_BANK(old_bank); + + DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", + __FUNCTION__, phyaddr, phyreg, phydata); + + return phydata; +} + +/* + * Writes a register to the MII Management serial interface + */ +static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, + int phydata) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int old_bank; + + /* Save the current bank, and select bank 3 */ + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(3); + + /* Idle - 32 ones */ + smc_mii_out(dev, 0xffffffff, 32); + + /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ + smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); + + /* Return to idle state */ + SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO)); + + /* And select original bank */ + SMC_SELECT_BANK(old_bank); + + DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", + __FUNCTION__, phyaddr, phyreg, phydata); +} + +/* + * Finds and reports the PHY address + */ +static void smc_detect_phy(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + int phyaddr; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + lp->phy_type = 0; + + /* + * Scan all 32 PHY addresses if necessary, starting at + * PHY#1 to PHY#31, and then PHY#0 last. + */ + for (phyaddr = 1; phyaddr < 33; ++phyaddr) { + unsigned int id1, id2; + + /* Read the PHY identifiers */ + id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); + id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); + + DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n", + dev->name, id1, id2); + + /* Make sure it is a valid identifier */ + if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && + id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { + /* Save the PHY's address */ + lp->mii.phy_id = phyaddr & 31; + lp->phy_type = id1 << 16 | id2; + break; + } + } +} + +/* + * Sets the PHY to a configuration as determined by the user + */ +static int smc_phy_fixed(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + int phyaddr = lp->mii.phy_id; + int bmcr, cfg1; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + /* Enter Link Disable state */ + cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); + cfg1 |= PHY_CFG1_LNKDIS; + smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); + + /* + * Set our fixed capabilities + * Disable auto-negotiation + */ + bmcr = 0; + + if (lp->ctl_rfduplx) + bmcr |= BMCR_FULLDPLX; + + if (lp->ctl_rspeed == 100) + bmcr |= BMCR_SPEED100; + + /* Write our capabilities to the phy control register */ + smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); + + /* Re-Configure the Receive/Phy Control register */ + SMC_SET_RPC(lp->rpc_cur_mode); + + return 1; +} + +/* + * smc_phy_reset - reset the phy + * @dev: net device + * @phy: phy address + * + * Issue a software reset for the specified PHY and + * wait up to 100ms for the reset to complete. We should + * not access the PHY for 50ms after issuing the reset. + * + * The time to wait appears to be dependent on the PHY. + * + * Must be called with lp->lock locked. + */ +static int smc_phy_reset(struct net_device *dev, int phy) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned int bmcr; + int timeout; + + smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); + + for (timeout = 2; timeout; timeout--) { + spin_unlock_irq(&lp->lock); + msleep(50); + spin_lock_irq(&lp->lock); + + bmcr = smc_phy_read(dev, phy, MII_BMCR); + if (!(bmcr & BMCR_RESET)) + break; + } + + return bmcr & BMCR_RESET; +} + +/* + * smc_phy_powerdown - powerdown phy + * @dev: net device + * @phy: phy address + * + * Power down the specified PHY + */ +static void smc_phy_powerdown(struct net_device *dev, int phy) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned int bmcr; + + spin_lock_irq(&lp->lock); + bmcr = smc_phy_read(dev, phy, MII_BMCR); + smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); + spin_unlock_irq(&lp->lock); +} + +/* + * smc_phy_check_media - check the media status and adjust TCR + * @dev: net device + * @init: set true for initialisation + * + * Select duplex mode depending on negotiation state. This + * also updates our carrier state. + */ +static void smc_phy_check_media(struct net_device *dev, int init) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + + if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { + unsigned int old_bank; + + /* duplex state has changed */ + if (lp->mii.full_duplex) { + lp->tcr_cur_mode |= TCR_SWFDUP; + } else { + lp->tcr_cur_mode &= ~TCR_SWFDUP; + } + + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(0); + SMC_SET_TCR(lp->tcr_cur_mode); + SMC_SELECT_BANK(old_bank); + } +} + +/* + * Configures the specified PHY through the MII management interface + * using Autonegotiation. + * Calls smc_phy_fixed() if the user has requested a certain config. + * If RPC ANEG bit is set, the media selection is dependent purely on + * the selection by the MII (either in the MII BMCR reg or the result + * of autonegotiation.) If the RPC ANEG bit is cleared, the selection + * is controlled by the RPC SPEED and RPC DPLX bits. + */ +static void smc_phy_configure(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + int phyaddr = lp->mii.phy_id; + int my_phy_caps; /* My PHY capabilities */ + int my_ad_caps; /* My Advertised capabilities */ + int status; + + DBG(3, "%s:smc_program_phy()\n", dev->name); + + spin_lock_irq(&lp->lock); + + /* + * We should not be called if phy_type is zero. + */ + if (lp->phy_type == 0) + goto smc_phy_configure_exit; + + if (smc_phy_reset(dev, phyaddr)) { + printk("%s: PHY reset timed out\n", dev->name); + goto smc_phy_configure_exit; + } + + /* + * Enable PHY Interrupts (for register 18) + * Interrupts listed here are disabled + */ + smc_phy_write(dev, phyaddr, PHY_MASK_REG, + PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | + PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | + PHY_INT_SPDDET | PHY_INT_DPLXDET); + + /* Configure the Receive/Phy Control register */ + SMC_SELECT_BANK(0); + SMC_SET_RPC(lp->rpc_cur_mode); + + /* If the user requested no auto neg, then go set his request */ + if (lp->mii.force_media) { + smc_phy_fixed(dev); + goto smc_phy_configure_exit; + } + + /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ + my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); + + if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { + printk(KERN_INFO "Auto negotiation NOT supported\n"); + smc_phy_fixed(dev); + goto smc_phy_configure_exit; + } + + my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ + + if (my_phy_caps & BMSR_100BASE4) + my_ad_caps |= ADVERTISE_100BASE4; + if (my_phy_caps & BMSR_100FULL) + my_ad_caps |= ADVERTISE_100FULL; + if (my_phy_caps & BMSR_100HALF) + my_ad_caps |= ADVERTISE_100HALF; + if (my_phy_caps & BMSR_10FULL) + my_ad_caps |= ADVERTISE_10FULL; + if (my_phy_caps & BMSR_10HALF) + my_ad_caps |= ADVERTISE_10HALF; + + /* Disable capabilities not selected by our user */ + if (lp->ctl_rspeed != 100) + my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); + + if (!lp->ctl_rfduplx) + my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); + + /* Update our Auto-Neg Advertisement Register */ + smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); + lp->mii.advertising = my_ad_caps; + + /* + * Read the register back. Without this, it appears that when + * auto-negotiation is restarted, sometimes it isn't ready and + * the link does not come up. + */ + status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); + + DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps); + DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps); + + /* Restart auto-negotiation process in order to advertise my caps */ + smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); + + smc_phy_check_media(dev, 1); + +smc_phy_configure_exit: + spin_unlock_irq(&lp->lock); +} + +/* + * smc_phy_interrupt + * + * Purpose: Handle interrupts relating to PHY register 18. This is + * called from the "hard" interrupt handler under our private spinlock. + */ +static void smc_phy_interrupt(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + int phyaddr = lp->mii.phy_id; + int phy18; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + if (lp->phy_type == 0) + return; + + for(;;) { + smc_phy_check_media(dev, 0); + + /* Read PHY Register 18, Status Output */ + phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); + if ((phy18 & PHY_INT_INT) == 0) + break; + } +} + +/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ + +static void smc_10bt_check_media(struct net_device *dev, int init) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + unsigned int old_carrier, new_carrier, old_bank; + + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(0); + old_carrier = netif_carrier_ok(dev) ? 1 : 0; + new_carrier = SMC_inw(ioaddr, EPH_STATUS_REG) & ES_LINK_OK ? 1 : 0; + + if (init || (old_carrier != new_carrier)) { + if (!new_carrier) { + netif_carrier_off(dev); + } else { + netif_carrier_on(dev); + } + if (netif_msg_link(lp)) + printk(KERN_INFO "%s: link %s\n", dev->name, + new_carrier ? "up" : "down"); + } + SMC_SELECT_BANK(old_bank); +} + +static void smc_eph_interrupt(struct net_device *dev) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int old_bank, ctl; + + smc_10bt_check_media(dev, 0); + + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(1); + + ctl = SMC_GET_CTL(); + SMC_SET_CTL(ctl & ~CTL_LE_ENABLE); + SMC_SET_CTL(ctl); + + SMC_SELECT_BANK(old_bank); +} + +/* + * This is the main routine of the driver, to handle the device when + * it needs some attention. + */ +static irqreturn_t smc_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct net_device *dev = dev_id; + unsigned long ioaddr = dev->base_addr; + struct smc_local *lp = netdev_priv(dev); + int status, mask, timeout, card_stats; + int saved_bank, saved_pointer; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + saved_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(2); + saved_pointer = SMC_GET_PTR(); + mask = SMC_GET_INT_MASK(); + SMC_SET_INT_MASK(0); + + /* set a timeout value, so I don't stay here forever */ + timeout = 8; + + do { + status = SMC_GET_INT(); + + DBG(2, "%s: IRQ 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", + dev->name, status, mask, + ({ int meminfo; SMC_SELECT_BANK(0); + meminfo = SMC_GET_MIR(); + SMC_SELECT_BANK(2); meminfo; }), + SMC_GET_FIFO()); + + status &= mask; + if (!status) + break; + + spin_lock(&lp->lock); + + if (status & IM_RCV_INT) { + DBG(3, "%s: RX irq\n", dev->name); + smc_rcv(dev); + } else if (status & IM_TX_INT) { + DBG(3, "%s: TX int\n", dev->name); + smc_tx(dev); + SMC_ACK_INT(IM_TX_INT); +#if THROTTLE_TX_PKTS + netif_wake_queue(dev); +#endif + } else if (status & IM_ALLOC_INT) { + DBG(3, "%s: Allocation irq\n", dev->name); + smc_hardware_send_packet(dev); + mask |= (IM_TX_INT | IM_TX_EMPTY_INT); + mask &= ~IM_ALLOC_INT; +#if ! THROTTLE_TX_PKTS + netif_wake_queue(dev); +#endif + } else if (status & IM_TX_EMPTY_INT) { + DBG(3, "%s: TX empty\n", dev->name); + mask &= ~IM_TX_EMPTY_INT; + + /* update stats */ + SMC_SELECT_BANK(0); + card_stats = SMC_GET_COUNTER(); + SMC_SELECT_BANK(2); + + /* single collisions */ + lp->stats.collisions += card_stats & 0xF; + card_stats >>= 4; + + /* multiple collisions */ + lp->stats.collisions += card_stats & 0xF; + } else if (status & IM_RX_OVRN_INT) { + DBG(1, "%s: RX overrun\n", dev->name); + SMC_ACK_INT(IM_RX_OVRN_INT); + lp->stats.rx_errors++; + lp->stats.rx_fifo_errors++; + } else if (status & IM_EPH_INT) { + smc_eph_interrupt(dev); + } else if (status & IM_MDINT) { + SMC_ACK_INT(IM_MDINT); + smc_phy_interrupt(dev); + } else if (status & IM_ERCV_INT) { + SMC_ACK_INT(IM_ERCV_INT); + PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name); + } + + spin_unlock(&lp->lock); + } while (--timeout); + + /* restore register states */ + SMC_SET_INT_MASK(mask); + SMC_SET_PTR(saved_pointer); + SMC_SELECT_BANK(saved_bank); + + DBG(3, "%s: Interrupt done (%d loops)\n", dev->name, 8-timeout); + + /* + * We return IRQ_HANDLED unconditionally here even if there was + * nothing to do. There is a possibility that a packet might + * get enqueued into the chip right after TX_EMPTY_INT is raised + * but just before the CPU acknowledges the IRQ. + * Better take an unneeded IRQ in some occasions than complexifying + * the code for all cases. + */ + return IRQ_HANDLED; +} + +/* Our watchdog timed out. Called by the networking layer */ +static void smc_timeout(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + smc_reset(dev); + smc_enable(dev); + +#if 0 + /* + * Reconfiguring the PHY doesn't seem like a bad idea here, but + * it introduced a problem. Now that this is a timeout routine, + * we are getting called from within an interrupt context. + * smc_phy_configure() calls msleep() which calls + * schedule_timeout() which calls schedule(). When schedule() + * is called from an interrupt context, it prints out + * "Scheduling in interrupt" and then calls BUG(). This is + * obviously not desirable. This was worked around by removing + * the call to smc_phy_configure() here because it didn't seem + * absolutely necessary. Ultimately, if msleep() is + * supposed to be usable from an interrupt context (which it + * looks like it thinks it should handle), it should be fixed. + */ + if (lp->phy_type != 0) + smc_phy_configure(dev); +#endif + + /* clear anything saved */ + if (lp->saved_skb != NULL) { + dev_kfree_skb (lp->saved_skb); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_aborted_errors++; + } + /* We can accept TX packets again */ + dev->trans_start = jiffies; + netif_wake_queue(dev); +} + +/* + * This sets the internal hardware table to filter out unwanted multicast + * packets before they take up memory. + * + * The SMC chip uses a hash table where the high 6 bits of the CRC of + * address are the offset into the table. If that bit is 1, then the + * multicast packet is accepted. Otherwise, it's dropped silently. + * + * To use the 6 bits as an offset into the table, the high 3 bits are the + * number of the 8 bit register, while the low 3 bits are the bit within + * that register. + * + * This routine is based very heavily on the one provided by Peter Cammaert. + */ +static void +smc_setmulticast(unsigned long ioaddr, int count, struct dev_mc_list *addrs) +{ + int i; + unsigned char multicast_table[8]; + struct dev_mc_list *cur_addr; + + /* table for flipping the order of 3 bits */ + static unsigned char invert3[] = { 0, 4, 2, 6, 1, 5, 3, 7 }; + + /* start with a table of all zeros: reject all */ + memset(multicast_table, 0, sizeof(multicast_table)); + + cur_addr = addrs; + for (i = 0; i < count; i++, cur_addr = cur_addr->next) { + int position; + + /* do we have a pointer here? */ + if (!cur_addr) + break; + /* make sure this is a multicast address - shouldn't this + be a given if we have it here ? */ + if (!(*cur_addr->dmi_addr & 1)) + continue; + + /* only use the low order bits */ + position = crc32_le(~0, cur_addr->dmi_addr, 6) & 0x3f; + + /* do some messy swapping to put the bit in the right spot */ + multicast_table[invert3[position&7]] |= + (1<>3)&7]); + + } + /* now, the table can be loaded into the chipset */ + SMC_SELECT_BANK(3); + SMC_SET_MCAST(multicast_table); +} + +/* + * This routine will, depending on the values passed to it, + * either make it accept multicast packets, go into + * promiscuous mode (for TCPDUMP and cousins) or accept + * a select set of multicast packets + */ +static void smc_set_multicast_list(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + SMC_SELECT_BANK(0); + if (dev->flags & IFF_PROMISC) { + DBG(2, "%s: RCR_PRMS\n", dev->name); + lp->rcr_cur_mode |= RCR_PRMS; + SMC_SET_RCR(lp->rcr_cur_mode); + } + +/* BUG? I never disable promiscuous mode if multicasting was turned on. + Now, I turn off promiscuous mode, but I don't do anything to multicasting + when promiscuous mode is turned on. +*/ + + /* + * Here, I am setting this to accept all multicast packets. + * I don't need to zero the multicast table, because the flag is + * checked before the table is + */ + else if (dev->flags & IFF_ALLMULTI || dev->mc_count > 16) { + lp->rcr_cur_mode |= RCR_ALMUL; + SMC_SET_RCR(lp->rcr_cur_mode); + DBG(2, "%s: RCR_ALMUL\n", dev->name); + } + + /* + * We just get all multicast packets even if we only want them + * from one source. This will be changed at some future point. + */ + else if (dev->mc_count) { + /* support hardware multicasting */ + + /* be sure I get rid of flags I might have set */ + lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); + SMC_SET_RCR(lp->rcr_cur_mode); + /* + * NOTE: this has to set the bank, so make sure it is the + * last thing called. The bank is set to zero at the top + */ + smc_setmulticast(ioaddr, dev->mc_count, dev->mc_list); + } else { + DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name); + lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); + SMC_SET_RCR(lp->rcr_cur_mode); + + /* + * since I'm disabling all multicast entirely, I need to + * clear the multicast list + */ + SMC_SELECT_BANK(3); + SMC_CLEAR_MCAST(); + } +} + + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc.. + */ +static int +smc_open(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + /* + * Check that the address is valid. If its not, refuse + * to bring the device up. The user must specify an + * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx + */ + if (!is_valid_ether_addr(dev->dev_addr)) { + DBG(2, (KERN_DEBUG "smc_open: no valid ethernet hw addr\n")); + return -EINVAL; + } + + /* clear out all the junk that was put here before... */ + lp->saved_skb = NULL; + + /* Setup the default Register Modes */ + lp->tcr_cur_mode = TCR_DEFAULT; + lp->rcr_cur_mode = RCR_DEFAULT; + lp->rpc_cur_mode = RPC_DEFAULT; + + /* + * If we are not using a MII interface, we need to + * monitor our own carrier signal to detect faults. + */ + if (lp->phy_type == 0) + lp->tcr_cur_mode |= TCR_MON_CSN; + + /* reset the hardware */ + smc_reset(dev); + smc_enable(dev); + + SMC_SELECT_BANK(1); + SMC_SET_MAC_ADDR(dev->dev_addr); + + /* Configure the PHY */ + if (lp->phy_type != 0) + smc_phy_configure(dev); + else { + spin_lock_irq(&lp->lock); + smc_10bt_check_media(dev, 1); + spin_unlock_irq(&lp->lock); + } + + /* + * make sure to initialize the link state with netif_carrier_off() + * somewhere, too --jgarzik + * + * smc_phy_configure() and smc_10bt_check_media() does that. --rmk + */ + netif_start_queue(dev); + return 0; +} + +/* + * smc_close + * + * this makes the board clean up everything that it can + * and not talk to the outside world. Caused by + * an 'ifconfig ethX down' + */ +static int smc_close(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + netif_stop_queue(dev); + netif_carrier_off(dev); + + /* clear everything */ + smc_shutdown(dev->base_addr); + + if (lp->phy_type != 0) + smc_phy_powerdown(dev, lp->mii.phy_id); + + return 0; +} + +/* + * Get the current statistics. + * This may be called with the card open or closed. + */ +static struct net_device_stats *smc_query_statistics(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + return &lp->stats; +} + +/* + * Ethtool support + */ +static int +smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct smc_local *lp = netdev_priv(dev); + int ret; + + cmd->maxtxpkt = 1; + cmd->maxrxpkt = 1; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_ethtool_gset(&lp->mii, cmd); + spin_unlock_irq(&lp->lock); + } else { + cmd->supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_TP | SUPPORTED_AUI; + + if (lp->ctl_rspeed == 10) + cmd->speed = SPEED_10; + else if (lp->ctl_rspeed == 100) + cmd->speed = SPEED_100; + + cmd->autoneg = AUTONEG_DISABLE; + cmd->transceiver = XCVR_INTERNAL; + cmd->port = 0; + cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF; + + ret = 0; + } + + return ret; +} + +static int +smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct smc_local *lp = netdev_priv(dev); + int ret; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_ethtool_sset(&lp->mii, cmd); + spin_unlock_irq(&lp->lock); + } else { + if (cmd->autoneg != AUTONEG_DISABLE || + cmd->speed != SPEED_10 || + (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) || + (cmd->port != PORT_TP && cmd->port != PORT_AUI)) + return -EINVAL; + +// lp->port = cmd->port; + lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL; + +// if (netif_running(dev)) +// smc_set_port(dev); + + ret = 0; + } + + return ret; +} + +static void +smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) +{ + strncpy(info->driver, CARDNAME, sizeof(info->driver)); + strncpy(info->version, version, sizeof(info->version)); + strncpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info)); +} + +static int smc_ethtool_nwayreset(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + int ret = -EINVAL; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_nway_restart(&lp->mii); + spin_unlock_irq(&lp->lock); + } + + return ret; +} + +static u32 smc_ethtool_getmsglevel(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return lp->msg_enable; +} + +static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) +{ + struct smc_local *lp = netdev_priv(dev); + lp->msg_enable = level; +} + +static struct ethtool_ops smc_ethtool_ops = { + .get_settings = smc_ethtool_getsettings, + .set_settings = smc_ethtool_setsettings, + .get_drvinfo = smc_ethtool_getdrvinfo, + + .get_msglevel = smc_ethtool_getmsglevel, + .set_msglevel = smc_ethtool_setmsglevel, + .nway_reset = smc_ethtool_nwayreset, + .get_link = ethtool_op_get_link, +// .get_eeprom = smc_ethtool_geteeprom, +// .set_eeprom = smc_ethtool_seteeprom, +}; + +/* + * smc_findirq + * + * This routine has a simple purpose -- make the SMC chip generate an + * interrupt, so an auto-detect routine can detect it, and find the IRQ, + */ +/* + * does this still work? + * + * I just deleted auto_irq.c, since it was never built... + * --jgarzik + */ +static int __init smc_findirq(unsigned long ioaddr) +{ + int timeout = 20; + unsigned long cookie; + + DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__); + + cookie = probe_irq_on(); + + /* + * What I try to do here is trigger an ALLOC_INT. This is done + * by allocating a small chunk of memory, which will give an interrupt + * when done. + */ + /* enable ALLOCation interrupts ONLY */ + SMC_SELECT_BANK(2); + SMC_SET_INT_MASK(IM_ALLOC_INT); + + /* + * Allocate 512 bytes of memory. Note that the chip was just + * reset so all the memory is available + */ + SMC_SET_MMU_CMD(MC_ALLOC | 1); + + /* + * Wait until positive that the interrupt has been generated + */ + do { + int int_status; + udelay(10); + int_status = SMC_GET_INT(); + if (int_status & IM_ALLOC_INT) + break; /* got the interrupt */ + } while (--timeout); + + /* + * there is really nothing that I can do here if timeout fails, + * as autoirq_report will return a 0 anyway, which is what I + * want in this case. Plus, the clean up is needed in both + * cases. + */ + + /* and disable all interrupts again */ + SMC_SET_INT_MASK(0); + + /* and return what I found */ + return probe_irq_off(cookie); +} + +/* + * Function: smc_probe(unsigned long ioaddr) + * + * Purpose: + * Tests to see if a given ioaddr points to an SMC91x chip. + * Returns a 0 on success + * + * Algorithm: + * (1) see if the high byte of BANK_SELECT is 0x33 + * (2) compare the ioaddr with the base register's address + * (3) see if I recognize the chip ID in the appropriate register + * + * Here I do typical initialization tasks. + * + * o Initialize the structure if needed + * o print out my vanity message if not done so already + * o print out what type of hardware is detected + * o print out the ethernet address + * o find the IRQ + * o set up my private data + * o configure the dev structure with my subroutines + * o actually GRAB the irq. + * o GRAB the region + */ +static int __init smc_probe(struct net_device *dev, unsigned long ioaddr) +{ + struct smc_local *lp = netdev_priv(dev); + static int version_printed = 0; + int i, retval; + unsigned int val, revision_register; + const char *version_string; + + DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__); + + /* First, see if the high byte is 0x33 */ + val = SMC_CURRENT_BANK(); + DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val); + if ((val & 0xFF00) != 0x3300) { + if ((val & 0xFF) == 0x33) { + printk(KERN_WARNING + "%s: Detected possible byte-swapped interface" + " at IOADDR 0x%lx\n", CARDNAME, ioaddr); + } + retval = -ENODEV; + goto err_out; + } + + /* + * The above MIGHT indicate a device, but I need to write to + * further test this. + */ + SMC_SELECT_BANK(0); + val = SMC_CURRENT_BANK(); + if ((val & 0xFF00) != 0x3300) { + retval = -ENODEV; + goto err_out; + } + + /* + * well, we've already written once, so hopefully another + * time won't hurt. This time, I need to switch the bank + * register to bank 1, so I can access the base address + * register + */ + SMC_SELECT_BANK(1); + val = SMC_GET_BASE(); + val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; + if ((ioaddr & ((PAGE_SIZE-1)<> 4) & 0xF]; + if (!version_string || (revision_register & 0xff00) != 0x3300) { + /* I don't recognize this chip, so... */ + printk("%s: IO 0x%lx: Unrecognized revision register 0x%04x" + ", Contact author.\n", CARDNAME, + ioaddr, revision_register); + + retval = -ENODEV; + goto err_out; + } + + /* At this point I'll assume that the chip is an SMC91x. */ + if (version_printed++ == 0) + printk("%s", version); + + /* fill in some of the fields */ + dev->base_addr = ioaddr; + lp->version = revision_register & 0xff; + + /* Get the MAC address */ + SMC_SELECT_BANK(1); + SMC_GET_MAC_ADDR(dev->dev_addr); + + /* now, reset the chip, and put it into a known state */ + smc_reset(dev); + + /* + * If dev->irq is 0, then the device has to be banged on to see + * what the IRQ is. + * + * This banging doesn't always detect the IRQ, for unknown reasons. + * a workaround is to reset the chip and try again. + * + * Interestingly, the DOS packet driver *SETS* the IRQ on the card to + * be what is requested on the command line. I don't do that, mostly + * because the card that I have uses a non-standard method of accessing + * the IRQs, and because this _should_ work in most configurations. + * + * Specifying an IRQ is done with the assumption that the user knows + * what (s)he is doing. No checking is done!!!! + */ + if (dev->irq < 1) { + int trials; + + trials = 3; + while (trials--) { + dev->irq = smc_findirq(ioaddr); + if (dev->irq) + break; + /* kick the card and try again */ + smc_reset(dev); + } + } + if (dev->irq == 0) { + printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n", + dev->name); + retval = -ENODEV; + goto err_out; + } + dev->irq = irq_canonicalize(dev->irq); + + /* Fill in the fields of the device structure with ethernet values. */ + ether_setup(dev); + + dev->open = smc_open; + dev->stop = smc_close; + dev->hard_start_xmit = smc_hard_start_xmit; + dev->tx_timeout = smc_timeout; + dev->watchdog_timeo = msecs_to_jiffies(watchdog); + dev->get_stats = smc_query_statistics; + dev->set_multicast_list = smc_set_multicast_list; + dev->ethtool_ops = &smc_ethtool_ops; + + spin_lock_init(&lp->lock); + lp->mii.phy_id_mask = 0x1f; + lp->mii.reg_num_mask = 0x1f; + lp->mii.force_media = 0; + lp->mii.full_duplex = 0; + lp->mii.dev = dev; + lp->mii.mdio_read = smc_phy_read; + lp->mii.mdio_write = smc_phy_write; + + /* + * Locate the phy, if any. + */ + if (lp->version >= (CHIP_91100 << 4)) + smc_detect_phy(dev); + + /* Set default parameters */ + lp->msg_enable = NETIF_MSG_LINK; + lp->ctl_rfduplx = 0; + lp->ctl_rspeed = 10; + + if (lp->version >= (CHIP_91100 << 4)) { + lp->ctl_rfduplx = 1; + lp->ctl_rspeed = 100; + } + + /* Grab the IRQ */ + retval = request_irq(dev->irq, &smc_interrupt, 0, dev->name, dev); + if (retval) + goto err_out; + + set_irq_type(dev->irq, IRQT_RISING); +#ifdef SMC_USE_PXA_DMA + { + int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW, + smc_pxa_dma_irq, NULL); + if (dma >= 0) + dev->dma = dma; + } +#endif + + retval = register_netdev(dev); + if (retval == 0) { + /* now, print out the card info, in a short format.. */ + printk("%s: %s (rev %d) at %#lx IRQ %d", + dev->name, version_string, revision_register & 0x0f, + dev->base_addr, dev->irq); + + if (dev->dma != (unsigned char)-1) + printk(" DMA %d", dev->dma); + + printk("%s%s\n", nowait ? " [nowait]" : "", + THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); + + if (!is_valid_ether_addr(dev->dev_addr)) { + printk("%s: Invalid ethernet MAC address. Please " + "set using ifconfig\n", dev->name); + } else { + /* Print the Ethernet address */ + printk("%s: Ethernet addr: ", dev->name); + for (i = 0; i < 5; i++) + printk("%2.2x:", dev->dev_addr[i]); + printk("%2.2x\n", dev->dev_addr[5]); + } + + if (lp->phy_type == 0) { + PRINTK("%s: No PHY found\n", dev->name); + } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { + PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name); + } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { + PRINTK("%s: PHY LAN83C180\n", dev->name); + } + } + +err_out: +#ifdef SMC_USE_PXA_DMA + if (retval && dev->dma != (unsigned char)-1) + pxa_free_dma(dev->dma); +#endif + return retval; +} + +static int smc_enable_device(unsigned long attrib_phys) +{ + unsigned long flags; + unsigned char ecor, ecsr; + void *addr; + + /* + * Map the attribute space. This is overkill, but clean. + */ + addr = ioremap(attrib_phys, ATTRIB_SIZE); + if (!addr) + return -ENOMEM; + + /* + * Reset the device. We must disable IRQs around this + * since a reset causes the IRQ line become active. + */ + local_irq_save(flags); + ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; + writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); + readb(addr + (ECOR << SMC_IO_SHIFT)); + + /* + * Wait 100us for the chip to reset. + */ + udelay(100); + + /* + * The device will ignore all writes to the enable bit while + * reset is asserted, even if the reset bit is cleared in the + * same write. Must clear reset first, then enable the device. + */ + writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); + writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); + + /* + * Set the appropriate byte/word mode. + */ + ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; +#ifndef SMC_CAN_USE_16BIT + ecsr |= ECSR_IOIS8; +#endif + writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); + local_irq_restore(flags); + + iounmap(addr); + + /* + * Wait for the chip to wake up. We could poll the control + * register in the main register space, but that isn't mapped + * yet. We know this is going to take 750us. + */ + msleep(1); + + return 0; +} + +/* + * smc_init(void) + * Input parameters: + * dev->base_addr == 0, try to find all possible locations + * dev->base_addr > 0x1ff, this is the address to check + * dev->base_addr == , return failure code + * + * Output: + * 0 --> there is a device + * anything else, error + */ +static int smc_drv_probe(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev; + struct resource *res, *ext = NULL; + unsigned int *addr; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENODEV; + goto out; + } + + /* + * Request the regions. + */ + if (!request_mem_region(res->start, SMC_IO_EXTENT, "smc91x")) { + ret = -EBUSY; + goto out; + } + + ndev = alloc_etherdev(sizeof(struct smc_local)); + if (!ndev) { + printk("%s: could not allocate device.\n", CARDNAME); + ret = -ENOMEM; + goto release_1; + } + SET_MODULE_OWNER(ndev); + SET_NETDEV_DEV(ndev, dev); + + ndev->dma = (unsigned char)-1; + ndev->irq = platform_get_irq(pdev, 0); + + ext = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (ext) { + if (!request_mem_region(ext->start, ATTRIB_SIZE, ndev->name)) { + ret = -EBUSY; + goto release_1; + } + +#if defined(CONFIG_SA1100_ASSABET) + NCR_0 |= NCR_ENET_OSC_EN; +#endif + + ret = smc_enable_device(ext->start); + if (ret) + goto release_both; + } + + addr = ioremap(res->start, SMC_IO_EXTENT); + if (!addr) { + ret = -ENOMEM; + goto release_both; + } + + dev_set_drvdata(dev, ndev); + ret = smc_probe(ndev, (unsigned long)addr); + if (ret != 0) { + dev_set_drvdata(dev, NULL); + iounmap(addr); + release_both: + if (ext) + release_mem_region(ext->start, ATTRIB_SIZE); + free_netdev(ndev); + release_1: + release_mem_region(res->start, SMC_IO_EXTENT); + out: + printk("%s: not found (%d).\n", CARDNAME, ret); + } +#ifdef SMC_USE_PXA_DMA + else { + struct smc_local *lp = netdev_priv(ndev); + lp->physaddr = res->start; + } +#endif + + return ret; +} + +static int smc_drv_remove(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev = dev_get_drvdata(dev); + struct resource *res; + + dev_set_drvdata(dev, NULL); + + unregister_netdev(ndev); + + free_irq(ndev->irq, ndev); + +#ifdef SMC_USE_PXA_DMA + if (ndev->dma != (unsigned char)-1) + pxa_free_dma(ndev->dma); +#endif + iounmap((void *)ndev->base_addr); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) + release_mem_region(res->start, ATTRIB_SIZE); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, SMC_IO_EXTENT); + + free_netdev(ndev); + + return 0; +} + +static int smc_drv_suspend(struct device *dev, u32 state, u32 level) +{ + struct net_device *ndev = dev_get_drvdata(dev); + + if (ndev && level == SUSPEND_DISABLE) { + if (netif_running(ndev)) { + netif_device_detach(ndev); + smc_shutdown(ndev->base_addr); + } + } + return 0; +} + +static int smc_drv_resume(struct device *dev, u32 level) +{ + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev = dev_get_drvdata(dev); + + if (ndev && level == RESUME_ENABLE) { + struct smc_local *lp = netdev_priv(ndev); + unsigned long ioaddr = ndev->base_addr; + + if (pdev->num_resources == 3) + smc_enable_device(pdev->resource[2].start); + if (netif_running(ndev)) { + smc_reset(ndev); + smc_enable(ndev); + SMC_SELECT_BANK(1); + SMC_SET_MAC_ADDR(ndev->dev_addr); + if (lp->phy_type != 0) + smc_phy_configure(ndev); + netif_device_attach(ndev); + } + } + return 0; +} + +static struct device_driver smc_driver = { + .name = CARDNAME, + .bus = &platform_bus_type, + .probe = smc_drv_probe, + .remove = smc_drv_remove, + .suspend = smc_drv_suspend, + .resume = smc_drv_resume, +}; + +static int __init smc_init(void) +{ +#ifdef MODULE + if (io == -1) + printk(KERN_WARNING + "%s: You shouldn't use auto-probing with insmod!\n", + CARDNAME); +#endif + + return driver_register(&smc_driver); +} + +static void __exit smc_cleanup(void) +{ + driver_unregister(&smc_driver); +} + +module_init(smc_init); +module_exit(smc_cleanup); diff -x .svn -urN linux-2.6.8-rc2/drivers/net/smc91x-bk16.h linux-2.6.8-rc2-pnp1/drivers/net/smc91x-bk16.h --- linux-2.6.8-rc2/drivers/net/smc91x-bk16.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/smc91x-bk16.h 2004-07-27 14:01:25.000000000 +0200 @@ -0,0 +1,866 @@ +/*------------------------------------------------------------------------ + . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. + . + . Copyright (C) 1996 by Erik Stahlman + . Copyright (C) 2001 Standard Microsystems Corporation + . Developed by Simple Network Magic Corporation + . Copyright (C) 2003 Monta Vista Software, Inc. + . Unified SMC91x driver by Nicolas Pitre + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . Authors + . Erik Stahlman + . Daris A Nevil + . Nicolas Pitre + . + ---------------------------------------------------------------------------*/ +#ifndef _SMC91X_H_ +#define _SMC91X_H_ + + +/* + * Define your architecture specific bus configuration parameters here. + */ + +#if defined(CONFIG_SA1100_GRAPHICSCLIENT) || \ + defined(CONFIG_SA1100_PFS168) || \ + defined(CONFIG_SA1100_FLEXANET) || \ + defined(CONFIG_SA1100_GRAPHICSMASTER) || \ + defined(CONFIG_ARCH_LUBBOCK) + +/* We can only do 16-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +/* The first two address lines aren't connected... */ +#define SMC_IO_SHIFT 2 + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) + +#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) + +/* We can only do 16-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +#define SMC_IO_SHIFT 0 + +#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) +#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) +#define SMC_insw(a, r, p, l) \ + do { \ + unsigned long __port = (a) + (r); \ + u16 *__p = (u16 *)(p); \ + int __l = (l); \ + insw(__port, __p, __l); \ + while (__l > 0) { \ + *__p = swab16(*__p); \ + __p++; \ + __l--; \ + } \ + } while (0) +#define SMC_outsw(a, r, p, l) \ + do { \ + unsigned long __port = (a) + (r); \ + u16 *__p = (u16 *)(p); \ + int __l = (l); \ + while (__l > 0) { \ + /* Believe it or not, the swab isn't needed. */ \ + outw( /* swab16 */ (*__p++), __port); \ + __l--; \ + } \ + } while (0) +#define set_irq_type(irq, type) + +#elif defined(CONFIG_SA1100_ASSABET) + +#include + +/* We can only do 8-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 0 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +/* The first two address lines aren't connected... */ +#define SMC_IO_SHIFT 2 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) +#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) + +#elif defined(CONFIG_ARCH_INNOKOM) || \ + defined(CONFIG_MACH_MAINSTONE) || \ + defined(CONFIG_ARCH_PXA_IDP) || \ + defined(CONFIG_ARCH_RAMSES) + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 1 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 +#define SMC_USE_PXA_DMA 1 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) +#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) + +/* We actually can't write halfwords properly if not word aligned */ +static inline void +SMC_outw(u16 val, unsigned long ioaddr, int reg) +{ + if (reg & 2) { + unsigned int v = val << 16; + v |= readl(ioaddr + (reg & ~2)) & 0xffff; + writel(v, ioaddr + (reg & ~2)); + } else { + writew(val, ioaddr + reg); + } +} + +#elif defined(CONFIG_ISA) + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 + +#define SMC_inb(a, r) inb((a) + (r)) +#define SMC_inw(a, r) inw((a) + (r)) +#define SMC_outb(v, a, r) outb(v, (a) + (r)) +#define SMC_outw(v, a, r) outw(v, (a) + (r)) +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#else + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 1 +#define SMC_NOWAIT 1 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) +#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) + +#define RPC_LSA_DEFAULT RPC_LED_100_10 +#define RPC_LSB_DEFAULT RPC_LED_TX_RX + +#endif + + +#ifdef SMC_USE_PXA_DMA +/* + * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is + * always happening in irq context so no need to worry about races. TX is + * different and probably not worth it for that reason, and not as critical + * as RX which can overrun memory and lose packets. + */ +#include +#include + +#ifdef SMC_insl +#undef SMC_insl +#define SMC_insl(a, r, p, l) \ + smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) +static inline void +smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma, + u_char *buf, int len) +{ + dma_addr_t dmabuf; + + /* fallback if no DMA available */ + if (dma == (unsigned char)-1) { + readsl(ioaddr + reg, buf, len); + return; + } + + /* 64 bit alignment is required for memory to memory DMA */ + if ((long)buf & 4) { + *((u32 *)buf)++ = SMC_inl(ioaddr, reg); + len--; + } + + len *= 4; + dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE); + DCSR(dma) = DCSR_NODESC; + DTADR(dma) = dmabuf; + DSADR(dma) = physaddr + reg; + DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | + DCMD_WIDTH4 | (DCMD_LENGTH & len)); + DCSR(dma) = DCSR_NODESC | DCSR_RUN; + while (!(DCSR(dma) & DCSR_STOPSTATE)); + DCSR(dma) = 0; + dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE); +} +#endif + +#ifdef SMC_insw +#undef SMC_insw +#define SMC_insw(a, r, p, l) \ + smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) +static inline void +smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma, + u_char *buf, int len) +{ + dma_addr_t dmabuf; + + /* fallback if no DMA available */ + if (dma == (unsigned char)-1) { + readsw(ioaddr + reg, buf, len); + return; + } + + /* 64 bit alignment is required for memory to memory DMA */ + while ((long)buf & 6) { + *((u16 *)buf)++ = SMC_inw(ioaddr, reg); + len--; + } + + len *= 2; + dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE); + DCSR(dma) = DCSR_NODESC; + DTADR(dma) = dmabuf; + DSADR(dma) = physaddr + reg; + DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | + DCMD_WIDTH2 | (DCMD_LENGTH & len)); + DCSR(dma) = DCSR_NODESC | DCSR_RUN; + while (!(DCSR(dma) & DCSR_STOPSTATE)); + DCSR(dma) = 0; + dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE); +} +#endif + +static void +smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs) +{ + DCSR(dma) = 0; +} +#endif /* SMC_USE_PXA_DMA */ + + +/* Because of bank switching, the LAN91x uses only 16 I/O ports */ +#ifndef SMC_IO_SHIFT +#define SMC_IO_SHIFT 0 +#endif +#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) + + +/* + . Bank Select Register: + . + . yyyy yyyy 0000 00xx + . xx = bank number + . yyyy yyyy = 0x33, for identification purposes. +*/ +#define BANK_SELECT (14 << SMC_IO_SHIFT) + + +// Transmit Control Register +/* BANK 0 */ +#define TCR_REG SMC_REG(0x0000, 0) +#define TCR_ENABLE 0x0001 // When 1 we can transmit +#define TCR_LOOP 0x0002 // Controls output pin LBK +#define TCR_FORCOL 0x0004 // When 1 will force a collision +#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 +#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames +#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier +#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation +#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error +#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback +#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode + +#define TCR_CLEAR 0 /* do NOTHING */ +/* the default settings for the TCR register : */ +#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) + + +// EPH Status Register +/* BANK 0 */ +#define EPH_STATUS_REG SMC_REG(0x0002, 0) +#define ES_TX_SUC 0x0001 // Last TX was successful +#define ES_SNGL_COL 0x0002 // Single collision detected for last tx +#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx +#define ES_LTX_MULT 0x0008 // Last tx was a multicast +#define ES_16COL 0x0010 // 16 Collisions Reached +#define ES_SQET 0x0020 // Signal Quality Error Test +#define ES_LTXBRD 0x0040 // Last tx was a broadcast +#define ES_TXDEFR 0x0080 // Transmit Deferred +#define ES_LATCOL 0x0200 // Late collision detected on last tx +#define ES_LOSTCARR 0x0400 // Lost Carrier Sense +#define ES_EXC_DEF 0x0800 // Excessive Deferral +#define ES_CTR_ROL 0x1000 // Counter Roll Over indication +#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin +#define ES_TXUNRN 0x8000 // Tx Underrun + + +// Receive Control Register +/* BANK 0 */ +#define RCR_REG SMC_REG(0x0004, 0) +#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted +#define RCR_PRMS 0x0002 // Enable promiscuous mode +#define RCR_ALMUL 0x0004 // When set accepts all multicast frames +#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets +#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets +#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision +#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier +#define RCR_SOFTRST 0x8000 // resets the chip + +/* the normal settings for the RCR register : */ +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) +#define RCR_CLEAR 0x0 // set it to a base state + + +// Counter Register +/* BANK 0 */ +#define COUNTER_REG SMC_REG(0x0006, 0) + + +// Memory Information Register +/* BANK 0 */ +#define MIR_REG SMC_REG(0x0008, 0) + + +// Receive/Phy Control Register +/* BANK 0 */ +#define RPC_REG SMC_REG(0x000A, 0) +#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. +#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode +#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode +#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb +#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb +#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect +#define RPC_LED_RES (0x01) // LED = Reserved +#define RPC_LED_10 (0x02) // LED = 10Mbps link detect +#define RPC_LED_FD (0x03) // LED = Full Duplex Mode +#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred +#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect +#define RPC_LED_TX (0x06) // LED = TX packet occurred +#define RPC_LED_RX (0x07) // LED = RX packet occurred + +#ifndef RPC_LSA_DEFAULT +#define RPC_LSA_DEFAULT RPC_LED_100 +#endif +#ifndef RPC_LSB_DEFAULT +#define RPC_LSB_DEFAULT RPC_LED_FD +#endif + +#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) + + +/* Bank 0 0x0C is reserved */ + +// Bank Select Register +/* All Banks */ +#define BSR_REG 0x000E + + +// Configuration Reg +/* BANK 1 */ +#define CONFIG_REG SMC_REG(0x0000, 1) +#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy +#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL +#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus +#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. + +// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low +#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) + + +// Base Address Register +/* BANK 1 */ +#define BASE_REG SMC_REG(0x0002, 1) + + +// Individual Address Registers +/* BANK 1 */ +#define ADDR0_REG SMC_REG(0x0004, 1) +#define ADDR1_REG SMC_REG(0x0006, 1) +#define ADDR2_REG SMC_REG(0x0008, 1) + + +// General Purpose Register +/* BANK 1 */ +#define GP_REG SMC_REG(0x000A, 1) + + +// Control Register +/* BANK 1 */ +#define CTL_REG SMC_REG(0x000C, 1) +#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received +#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically +#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt +#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt +#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt +#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store +#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers +#define CTL_STORE 0x0001 // When set stores registers into EEPROM + + +// MMU Command Register +/* BANK 2 */ +#define MMU_CMD_REG SMC_REG(0x0000, 2) +#define MC_BUSY 1 // When 1 the last release has not completed +#define MC_NOP (0<<5) // No Op +#define MC_ALLOC (1<<5) // OR with number of 256 byte packets +#define MC_RESET (2<<5) // Reset MMU to initial state +#define MC_REMOVE (3<<5) // Remove the current rx packet +#define MC_RELEASE (4<<5) // Remove and release the current rx packet +#define MC_FREEPKT (5<<5) // Release packet in PNR register +#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit +#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs + + +// Packet Number Register +/* BANK 2 */ +#define PN_REG SMC_REG(0x0002, 2) + + +// Allocation Result Register +/* BANK 2 */ +#define AR_REG SMC_REG(0x0003, 2) +#define AR_FAILED 0x80 // Alocation Failed + + +// TX FIFO Ports Register +/* BANK 2 */ +#define TXFIFO_REG SMC_REG(0x0004, 2) +#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty + +// RX FIFO Ports Register +/* BANK 2 */ +#define RXFIFO_REG SMC_REG(0x0005, 2) +#define RXFIFO_REMPTY 0x80 // RX FIFO Empty + +#define FIFO_REG SMC_REG(0x0004, 2) + +// Pointer Register +/* BANK 2 */ +#define PTR_REG SMC_REG(0x0006, 2) +#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area +#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access +#define PTR_READ 0x2000 // When 1 the operation is a read + + +// Data Register +/* BANK 2 */ +#define DATA_REG SMC_REG(0x0008, 2) + + +// Interrupt Status/Acknowledge Register +/* BANK 2 */ +#define INT_REG SMC_REG(0x000C, 2) + + +// Interrupt Mask Register +/* BANK 2 */ +#define IM_REG SMC_REG(0x000D, 2) +#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt +#define IM_ERCV_INT 0x40 // Early Receive Interrupt +#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section +#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns +#define IM_ALLOC_INT 0x08 // Set when allocation request is completed +#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty +#define IM_TX_INT 0x02 // Transmit Interrupt +#define IM_RCV_INT 0x01 // Receive Interrupt + + +// Multicast Table Registers +/* BANK 3 */ +#define MCAST_REG1 SMC_REG(0x0000, 3) +#define MCAST_REG2 SMC_REG(0x0002, 3) +#define MCAST_REG3 SMC_REG(0x0004, 3) +#define MCAST_REG4 SMC_REG(0x0006, 3) + + +// Management Interface Register (MII) +/* BANK 3 */ +#define MII_REG SMC_REG(0x0008, 3) +#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup +#define MII_MDOE 0x0008 // MII Output Enable +#define MII_MCLK 0x0004 // MII Clock, pin MDCLK +#define MII_MDI 0x0002 // MII Input, pin MDI +#define MII_MDO 0x0001 // MII Output, pin MDO + + +// Revision Register +/* BANK 3 */ +/* ( hi: chip id low: rev # ) */ +#define REV_REG SMC_REG(0x000A, 3) + + +// Early RCV Register +/* BANK 3 */ +/* this is NOT on SMC9192 */ +#define ERCV_REG SMC_REG(0x000C, 3) +#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received +#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask + + +// External Register +/* BANK 7 */ +#define EXT_REG SMC_REG(0x0000, 7) + + +#define CHIP_9192 3 +#define CHIP_9194 4 +#define CHIP_9195 5 +#define CHIP_9196 6 +#define CHIP_91100 7 +#define CHIP_91100FD 8 +#define CHIP_91111FD 9 + +static const char * chip_ids[ 16 ] = { + NULL, NULL, NULL, + /* 3 */ "SMC91C90/91C92", + /* 4 */ "SMC91C94", + /* 5 */ "SMC91C95", + /* 6 */ "SMC91C96", + /* 7 */ "SMC91C100", + /* 8 */ "SMC91C100FD", + /* 9 */ "SMC91C11xFD", + NULL, NULL, NULL, + NULL, NULL, NULL}; + + +/* + . Transmit status bits +*/ +#define TS_SUCCESS 0x0001 +#define TS_LOSTCAR 0x0400 +#define TS_LATCOL 0x0200 +#define TS_16COL 0x0010 + +/* + . Receive status bits +*/ +#define RS_ALGNERR 0x8000 +#define RS_BRODCAST 0x4000 +#define RS_BADCRC 0x2000 +#define RS_ODDFRAME 0x1000 +#define RS_TOOLONG 0x0800 +#define RS_TOOSHORT 0x0400 +#define RS_MULTICAST 0x0001 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) + + +/* + * PHY IDs + * LAN83C183 == LAN91C111 Internal PHY + */ +#define PHY_LAN83C183 0x0016f840 +#define PHY_LAN83C180 0x02821c50 + +/* + * PHY Register Addresses (LAN91C111 Internal PHY) + * + * Generic PHY registers can be found in + * + * These phy registers are specific to our on-board phy. + */ + +// PHY Configuration Register 1 +#define PHY_CFG1_REG 0x10 +#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled +#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled +#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down +#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler +#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable +#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled +#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) +#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db +#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time + + +// PHY Configuration Register 2 +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled +#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled +#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) +#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo + +// PHY Status Output (and Interrupt status) Register +#define PHY_INT_REG 0x12 // Status Output (Interrupt Status) +#define PHY_INT_INT 0x8000 // 1=bits have changed since last read +#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected +#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync +#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx +#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx +#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx +#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected +#define PHY_INT_JAB 0x0100 // 1=Jabber detected +#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode +#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex + +// PHY Interrupt/Status Mask Register +#define PHY_MASK_REG 0x13 // Interrupt Mask +// Uses the same bit definitions as PHY_INT_REG + + +/* + * SMC91C96 ethernet config and status registers. + * These are in the "attribute" space. + */ +#define ECOR 0x8000 +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x04 +#define ECOR_ENABLE 0x01 + +#define ECSR 0x8002 +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 + +#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) + + +/* + * Macros to abstract register access according to the data bus + * capabilities. Please use those and not the in/out primitives. + * Note: the following macros do *not* select the bank -- this must + * be done separately as needed in the main code. The SMC_REG() macro + * only uses the bank argument for debugging purposes (when enabled). + */ + +#if SMC_DEBUG > 0 +#define SMC_REG(reg, bank) \ + ({ \ + int __b = SMC_CURRENT_BANK(); \ + if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ + printk( "%s: bank reg screwed (0x%04x)\n", \ + CARDNAME, __b ); \ + BUG(); \ + } \ + reg<> 8) +#define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF) +#define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8) +#define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF) +#define SMC_ACK_INT(x) \ + do { \ + unsigned long __flags; \ + int __mask; \ + local_irq_save(__flags); \ + __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ + SMC_outw( __mask | (x), ioaddr, INT_REG ); \ + local_irq_restore(__flags); \ + } while (0) +#define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8) +#define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG ) +#endif + +#define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT ) +#define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT ) +#define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG ) +#define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG ) +#define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG ) +#define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG ) +#define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG ) +#define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG ) +#define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG ) +#define SMC_GET_MII() SMC_inw( ioaddr, MII_REG ) +#define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG ) +#define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG ) +#define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG ) +#define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG ) +#define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG ) +#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG ) +#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG ) +#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG ) +#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG ) +#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG ) +#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG ) +#define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG ) +#define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG ) +#define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG ) +#define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG ) + +#ifndef SMC_GET_MAC_ADDR +#define SMC_GET_MAC_ADDR(addr) \ + do { \ + unsigned int __v; \ + __v = SMC_inw( ioaddr, ADDR0_REG ); \ + addr[0] = __v; addr[1] = __v >> 8; \ + __v = SMC_inw( ioaddr, ADDR1_REG ); \ + addr[2] = __v; addr[3] = __v >> 8; \ + __v = SMC_inw( ioaddr, ADDR2_REG ); \ + addr[4] = __v; addr[5] = __v >> 8; \ + } while (0) +#endif + +#define SMC_SET_MAC_ADDR(addr) \ + do { \ + SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ + SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ + SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ + } while (0) + +#define SMC_CLEAR_MCAST() \ + do { \ + SMC_outw( 0, ioaddr, MCAST_REG1 ); \ + SMC_outw( 0, ioaddr, MCAST_REG2 ); \ + SMC_outw( 0, ioaddr, MCAST_REG3 ); \ + SMC_outw( 0, ioaddr, MCAST_REG4 ); \ + } while (0) +#define SMC_SET_MCAST(x) \ + do { \ + unsigned char *mt = (x); \ + SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ + SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ + SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ + SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ + } while (0) + +#if SMC_CAN_USE_32BIT +/* + * Some setups just can't write 8 or 16 bits reliably when not aligned + * to a 32 bit boundary. I tell you that exists! + * We re-do the ones here that can be easily worked around if they can have + * their low parts written to 0 without adverse effects. + */ +#undef SMC_SELECT_BANK +#define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<> 16; \ + } while (0) +#else +#define SMC_PUT_PKT_HDR(status, length) \ + do { \ + SMC_outw( status, ioaddr, DATA_REG ); \ + SMC_outw( length, ioaddr, DATA_REG ); \ + } while (0) +#define SMC_GET_PKT_HDR(status, length) \ + do { \ + (status) = SMC_inw( ioaddr, DATA_REG ); \ + (length) = SMC_inw( ioaddr, DATA_REG ); \ + } while (0) +#endif + +#if SMC_CAN_USE_32BIT +#define SMC_PUSH_DATA(p, l) \ + do { \ + char *__ptr = (p); \ + int __len = (l); \ + if (__len >= 2 && (long)__ptr & 2) { \ + __len -= 2; \ + SMC_outw( *((u16 *)__ptr)++, ioaddr, DATA_REG );\ + } \ + SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \ + if (__len & 2) { \ + __ptr += (__len & ~3); \ + SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ + } \ + } while (0) +#define SMC_PULL_DATA(p, l) \ + do { \ + char *__ptr = (p); \ + int __len = (l); \ + if ((long)__ptr & 2) { \ + /* \ + * We want 32bit alignment here. \ + * Since some buses perform a full 32bit \ + * fetch even for 16bit data we can't use \ + * SMC_inw() here. Back both source (on chip \ + * and destination) pointers of 2 bytes. \ + */ \ + (long)__ptr &= ~2; \ + __len += 2; \ + SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \ + } \ + __len += 2; \ + SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \ + } while (0) +#elif SMC_CAN_USE_16BIT +#define SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 ) +#define SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 ) +#elif SMC_CAN_USE_8BIT +#define SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l ) +#define SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l ) +#endif + +#if ! SMC_CAN_USE_16BIT +#define SMC_outw(x, ioaddr, reg) \ + do { \ + unsigned int __val16 = (x); \ + SMC_outb( __val16, ioaddr, reg ); \ + SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ + } while (0) +#define SMC_inw(ioaddr, reg) \ + ({ \ + unsigned int __val16; \ + __val16 = SMC_inb( ioaddr, reg ); \ + __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ + __val16; \ + }) +#endif + + +#endif /* _SMC91X_H_ */ diff -x .svn -urN linux-2.6.8-rc2/drivers/net/smc91x.h linux-2.6.8-rc2-pnp1/drivers/net/smc91x.h --- linux-2.6.8-rc2/drivers/net/smc91x.h 2004-07-27 14:08:05.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/drivers/net/smc91x.h 2004-07-27 14:01:27.000000000 +0200 @@ -117,7 +117,8 @@ #elif defined(CONFIG_ARCH_INNOKOM) || \ defined(CONFIG_MACH_MAINSTONE) || \ defined(CONFIG_ARCH_PXA_IDP) || \ - defined(CONFIG_ARCH_RAMSES) + defined(CONFIG_ARCH_RAMSES) || \ + defined(CONFIG_ARCH_PXA_PNP2110) #define SMC_CAN_USE_8BIT 1 #define SMC_CAN_USE_16BIT 1 diff -x .svn -urN linux-2.6.8-rc2/drivers/net/smc91x-new-hal.c linux-2.6.8-rc2-pnp1/drivers/net/smc91x-new-hal.c --- linux-2.6.8-rc2/drivers/net/smc91x-new-hal.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/smc91x-new-hal.c 2004-07-27 14:01:19.000000000 +0200 @@ -0,0 +1,2125 @@ +/* + * Smc91x.c + * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. + * + * Copyright (C) 1996 by Erik Stahlman + * Copyright (C) 2001 Standard Microsystems Corporation + * Developed by Simple Network Magic Corporation + * Copyright (C) 2003 Monta Vista Software, Inc. + * Unified SMC91x driver by Nicolas Pitre + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Arguments: + * io = for the base address + * irq = for the IRQ + * nowait = 0 for normal wait states, 1 eliminates additional wait states + * + * original author: + * Erik Stahlman + * + * hardware multicast code: + * Peter Cammaert + * + * contributors: + * Daris A Nevil + * Nicolas Pitre + * Russell King + * + * History: + * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet + * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" + * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 + * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 + * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 + * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support + * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, + * more bus abstraction, big cleanup, etc. + * 29/09/03 Russell King - add driver model support + * - ethtool support + * - convert to use generic MII interface + * - add link up/down notification + * - don't try to handle full negotiation in + * smc_phy_configure + * - clean up (and fix stack overrun) in PHY + * MII read/write functions + */ + +/* + * HAL rewrite by Robert Schwebel + * + * FIXME: + * + * - SMC_DISABLE_INT() is never used in bk17 driver + * + */ + +static const char version[] = + "smc91x.c: v1.0, mar 07 2003 by Nicolas Pitre \n"; + +/* Debugging level */ +#ifndef SMC_DEBUG +#define SMC_DEBUG 0 +#endif + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#ifdef CONFIG_ARM +#include +#endif +#include + +#include "smc91x.h" + +#ifdef CONFIG_ISA +/* + * the LAN91C111 can be at any of the following port addresses. To change, + * for a slightly different card, you can add it to the array. Keep in + * mind that the array must end in zero. + */ +static unsigned int smc_portlist[] __initdata = { + 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0, + 0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0, 0 +}; + +#ifndef SMC_IOADDR +# define SMC_IOADDR -1 +#endif +static unsigned long io = SMC_IOADDR; +module_param(io, ulong, 0400); +MODULE_PARM_DESC(io, "I/O base address"); + +#ifndef SMC_IRQ +# define SMC_IRQ -1 +#endif +static int irq = SMC_IRQ; +module_param(irq, int, 0400); +MODULE_PARM_DESC(irq, "IRQ number"); + +#endif /* CONFIG_ISA */ + +#ifndef SMC_NOWAIT +# define SMC_NOWAIT 0 +#endif +static int nowait = SMC_NOWAIT; +module_param(nowait, int, 0400); +MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); + +/* + * Transmit timeout, default 5 seconds. + */ +static int watchdog = 5000; +module_param(watchdog, int, 0400); +MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); + +MODULE_LICENSE("GPL"); + +/* + * The internal workings of the driver. If you are changing anything + * here with the SMC stuff, you should have the datasheet and know + * what you are doing. + */ +#define CARDNAME "smc91x" + +/* + * Use power-down feature of the chip + */ +#define POWER_DOWN 1 + +/* + * Wait time for memory to be free. This probably shouldn't be + * tuned that much, as waiting for this means nothing else happens + * in the system + */ +#define MEMORY_WAIT_TIME 16 + +/* + * This selects whether TX packets are sent one by one to the SMC91x internal + * memory and throttled until transmission completes. This may prevent + * RX overruns a litle by keeping much of the memory free for RX packets + * but to the expense of reduced TX throughput and increased IRQ overhead. + * Note this is not a cure for a too slow data bus or too high IRQ latency. + */ +#define THROTTLE_TX_PKTS 0 + +/* + * The MII clock high/low times. 2x this number gives the MII clock period + * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) + */ +#define MII_DELAY 1 + +/* FIXME: add KERN_DEBUG */ + + #if SMC_DEBUG > 0 +#define DBG(n, args...) \ + do { \ + if (SMC_DEBUG >= (n)) \ + printk(args); \ + } while (0) + +#define PRINTK(args...) printk(args) +#else +#define DBG(n, args...) do { } while(0) +#define PRINTK(args...) printk(args) +#endif + +#if SMC_DEBUG > 3 +static void PRINT_PKT(unsigned char *buf, u16 length) +{ + int i; + int remainder; + int lines; + + lines = length / 16; + remainder = length % 16; + + for (i = 0; i < lines ; i ++) { + int cur; + for (cur = 0; cur < 8; cur++) { + u_char a, b; + a = *buf++; + b = *buf++; + printk("%02x%02x ", a, b); + } + printk("\n"); + } + for (i = 0; i < remainder/2 ; i++) { + u_char a, b; + a = *buf++; + b = *buf++; + printk("%02x%02x ", a, b); + } + printk("\n"); +} +#else +#define PRINT_PKT(x...) do { } while(0) +#endif + +/* + * this does a soft reset on the device + */ +static void smc_reset(struct net_device *dev) +{ + unsigned int ctl, cfg; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + /* + * This resets the registers mostly to defaults, but doesn't + * affect EEPROM. That seems unnecessary + */ + smc_select_bank(dev, 0); + smc_set_rcr(dev, RCR_SOFTRST); + + /* + * Setup the Configuration Register + * This is necessary because the CONFIG_REG is not affected + * by a soft reset + */ + smc_select_bank(dev, 1); + + cfg = CONFIGREG_DEFAULT; + + /* + * Setup for fast accesses if requested. If the card/system + * can't handle it then there will be no recovery except for + * a hard reset or power cycle + */ + if (nowait) + cfg |= CONFIG_NO_WAIT; + + /* + * Release from possible power-down state + * Configuration register is not affected by Soft Reset + */ + cfg |= CONFIG_EPH_PWR_EN; + + smc_set_config(dev, cfg); + + /* this should pause enough for the chip to be happy */ + /* + * elaborate? What does the chip _need_? --jgarzik + * + * This seems to be undocumented, but something the original + * driver(s) have always done. Suspect undocumented timing + * info/determined empirically. --rmk + */ + udelay(1); + + /* Disable transmit and receive functionality */ + smc_select_bank(dev, 0); + smc_set_rcr(dev, RCR_CLEAR); + smc_set_tcr(dev, TCR_CLEAR); + + smc_select_bank(dev, 1); + ctl = smc_get_ctl(dev) | CTL_LE_ENABLE; + + /* + * Set the control register to automatically release successfully + * transmitted packets, to make the best use out of our limited + * memory + */ +#if ! THROTTLE_TX_PKTS + ctl |= CTL_AUTO_REL; +#else + ctl &= ~CTL_AUTO_REL; +#endif + smc_set_ctl(dev, ctl); + + /* Disable all interrupts */ + smc_select_bank(dev, 2); + smc_set_int_mask(dev, 0); + + /* Reset the MMU */ + smc_set_mmu_cmd(dev, MC_RESET); + smc_wait_mmu_busy(dev); +} + +/* + * Enable Interrupts, Receive, and Transmit + */ +static void smc_enable(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + int mask; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + /* see the header file for options in TCR/RCR DEFAULT */ + smc_select_bank(dev, 0); + smc_set_tcr(dev, lp->tcr_cur_mode); + smc_set_rcr(dev, lp->rcr_cur_mode); + + /* now, enable interrupts */ + mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; + if (lp->version >= (CHIP_91100 << 4)) + mask |= IM_MDINT; + smc_select_bank(dev, 2); + smc_set_int_mask(dev, mask); +} + +/* + * this puts the device in an inactive state + */ +static void smc_shutdown(struct net_device *dev) +{ + DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__); + + /* no more interrupts for me */ + smc_select_bank(dev, 2); + smc_set_int_mask(dev, 0); + + /* and tell the card to stay away from that nasty outside world */ + smc_select_bank(dev, 0); + smc_set_rcr(dev, RCR_CLEAR); + smc_set_tcr(dev, TCR_CLEAR); + +#ifdef POWER_DOWN + /* finally, shut the chip down */ + smc_select_bank(dev, 1); + smc_set_config(dev, smc_get_config(dev) & ~CONFIG_EPH_PWR_EN); +#endif +} + +/* + * This is the procedure to handle the receipt of a packet. + */ +static inline void smc_rcv(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + u16 packet_number, status, packet_len; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + packet_number = smc_get_rxfifo(dev); + if (unlikely(packet_number & RXFIFO_REMPTY)) { + PRINTK("%s: smc_rcv with nothing on FIFO (0x%04x).\n", + dev->name, packet_number); + return; + } + + /* read from start of packet */ + smc_set_ptr(dev, PTR_READ | PTR_RCV | PTR_AUTOINC); + + /* First two words are status and packet length */ + smc_get_pkt_hdr(dev, &status, &packet_len); + packet_len &= 0x07ff; /* mask off top bits */ + DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", + dev->name, packet_number, status, + packet_len, packet_len); + + if (unlikely(status & RS_ERRORS)) { + lp->stats.rx_errors++; + if (status & RS_ALGNERR) + lp->stats.rx_frame_errors++; + if (status & (RS_TOOSHORT | RS_TOOLONG)) + lp->stats.rx_length_errors++; + if (status & RS_BADCRC) + lp->stats.rx_crc_errors++; + } else { + struct sk_buff *skb; + unsigned char *data; + u16 data_len; + + /* set multicast stats */ + if (status & RS_MULTICAST) + lp->stats.multicast++; + + /* + * Actual payload is packet_len - 4 (or 3 if odd byte). + * We want skb_reserve(2) and the final ctrl word + * (2 bytes, possibly containing the payload odd byte). + * Ence packet_len - 4 + 2 + 2. + */ + skb = dev_alloc_skb(packet_len); + if (unlikely(skb == NULL)) { + printk(KERN_NOTICE "%s: Low memory, packet dropped.\n", + dev->name); + lp->stats.rx_dropped++; + goto done; + } + + /* Align IP header to 32 bits */ + skb_reserve(skb, 2); + + /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ + if (lp->version == 0x90) + status |= RS_ODDFRAME; + + /* + * If odd length: packet_len - 3, + * otherwise packet_len - 4. + */ + data_len = packet_len - ((status & RS_ODDFRAME) ? 3 : 4); + data = skb_put(skb, data_len); + smc_pull_data(dev, data, packet_len - 2); + + PRINT_PKT(data, packet_len - 2); + + dev->last_rx = jiffies; + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + lp->stats.rx_packets++; + lp->stats.rx_bytes += data_len; + } + +done: + smc_wait_mmu_busy(dev); + smc_set_mmu_cmd(dev, MC_RELEASE); +} + +/* + * This is called to actually send a packet to the chip. + * Returns non-zero when successful. + */ +static void smc_hardware_send_packet(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + struct sk_buff *skb = lp->saved_skb; + u16 packet_no, len; + unsigned char *buf; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + packet_no = smc_get_ar(dev); + if (unlikely(packet_no & AR_FAILED)) { + printk("%s: Memory allocation failed.\n", dev->name); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_fifo_errors++; + dev_kfree_skb_any(skb); + return; + } + + /* point to the beginning of the packet */ + smc_set_pn(dev, packet_no); + smc_set_ptr(dev, PTR_AUTOINC); + + buf = skb->data; + len = skb->len; + DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", + dev->name, packet_no, len, len, buf); + PRINT_PKT(buf, len); + + /* + * Send the packet length (+6 for status words, length, and ctl. + * The card will pad to 64 bytes with zeroes if packet is too small. + */ + smc_put_pkt_hdr(dev, 0, len + 6); + + /* send the actual data */ + smc_push_data(dev, buf, len & ~1); + + /* Send final ctl word with the last byte if there is one */ + writew(((len & 1) ? (0x2000 | buf[len-1]) : 0), + lp->ioaddr + (SMC_REG_DATA<addrshift)); + + /* and let the chipset deal with it */ + smc_set_mmu_cmd(dev, MC_ENQUEUE); + smc_ack_int(dev, IM_TX_EMPTY_INT); + + smc_enable_int(dev,IM_TX_INT | IM_TX_EMPTY_INT); + dev->trans_start = jiffies; + dev_kfree_skb_any(skb); + lp->saved_skb = NULL; + lp->stats.tx_packets++; + lp->stats.tx_bytes += len; +} + +/* + * Since I am not sure if I will have enough room in the chip's ram + * to store the packet, I call this routine which either sends it + * now, or set the card to generates an interrupt when ready + * for the packet. + */ +static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + u16 numPages, poll_count, status, saved_bank, mask; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + BUG_ON(lp->saved_skb != NULL); + lp->saved_skb = skb; + + /* + * The MMU wants the number of pages to be the number of 256 bytes + * 'pages', minus 1 (since a packet can't ever have 0 pages :)) + * + * The 91C111 ignores the size bits, but earlier models don't. + * + * Pkt size for allocating is data length +6 (for additional status + * words, length and ctl) + * + * If odd size then last byte is included in ctl word. + */ + numPages = ((skb->len & ~1) + (6 - 1)) >> 8; + if (unlikely(numPages > 7)) { + printk("%s: Far too big packet error.\n", dev->name); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_dropped++; + dev_kfree_skb(skb); + return 0; + } + + /* now, try to allocate the memory */ + saved_bank = smc_current_bank(dev); + smc_select_bank(dev, 2); + smc_set_mmu_cmd(dev, MC_ALLOC | numPages); + + /* + * Poll the chip for a short amount of time in case the + * allocation succeeds quickly. + */ + poll_count = MEMORY_WAIT_TIME; + do { + status = smc_get_int(dev); + if (status & IM_ALLOC_INT) { + smc_ack_int(dev, IM_ALLOC_INT); + break; + } + } while (--poll_count); + + if (!poll_count) { + /* oh well, wait until the chip finds memory later */ + netif_stop_queue(dev); + DBG(2, "%s: TX memory allocation deferred.\n", dev->name); + smc_enable_int(dev,IM_ALLOC_INT); + } else { + /* + * Allocation succeeded: push packet to the chip's own memory + * immediately. + * + * If THROTTLE_TX_PKTS is selected that means we don't want + * more than a single TX packet taking up space in the chip's + * internal memory at all time, in which case we stop the + * queue right here until we're notified of TX completion. + * + * Otherwise we're quite happy to feed more TX packets right + * away for better TX throughput, in which case the queue is + * left active. + */ +#if THROTTLE_TX_PKTS + netif_stop_queue(dev); +#endif + status = smc_get_int(dev); + mask = smc_get_int_mask(dev); + + smc_hardware_send_packet(dev); + } + + smc_select_bank(dev, saved_bank); + return 0; +} + +/* + * This handles a TX interrupt, which is only called when: + * - a TX error occurred, or + * - CTL_AUTO_RELEASE is not set and TX of a packet completed. + */ +static void smc_tx(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + u16 saved_packet, packet_no, tx_status, pkt_len; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + /* If the TX FIFO is empty then nothing to do */ + packet_no = smc_get_txfifo(dev); + if (unlikely(packet_no & TXFIFO_TEMPTY)) { + PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name); + return; + } + + /* select packet to read from */ + saved_packet = smc_get_pn(dev); + smc_set_pn(dev, packet_no); + + /* read the first word (status word) from this packet */ + smc_set_ptr(dev, PTR_AUTOINC | PTR_READ); + smc_get_pkt_hdr(dev, &tx_status, &pkt_len); + DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n", + dev->name, tx_status, packet_no); + + if (!(tx_status & TS_SUCCESS)) + lp->stats.tx_errors++; + if (tx_status & TS_LOSTCAR) + lp->stats.tx_carrier_errors++; + + smc_wait_mmu_busy(dev); + + if (tx_status & TS_LATCOL) { + PRINTK("%s: late collision occurred on last xmit\n", dev->name); + lp->stats.tx_window_errors++; + /* It's really cheap to requeue the pkt here */ + smc_set_mmu_cmd(dev, MC_ENQUEUE ); + } else { + /* kill the packet */ + smc_set_mmu_cmd(dev, MC_FREEPKT); + } + + /* Don't restore Packet Number Reg until busy bit is cleared */ + smc_wait_mmu_busy(dev); + smc_set_pn(dev, saved_packet); + + /* re-enable transmit */ + smc_select_bank(dev, 0); + smc_set_tcr(dev, lp->tcr_cur_mode); + smc_select_bank(dev, 2); +} + + +/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ + +static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) +{ + unsigned int mii_reg, mask; + + mii_reg = smc_get_mii(dev) & ~(MII_MCLK | MII_MDOE | MII_MDO); + mii_reg |= MII_MDOE; + + for (mask = 1 << (bits - 1); mask; mask >>= 1) { + if (val & mask) + mii_reg |= MII_MDO; + else + mii_reg &= ~MII_MDO; + + smc_set_mii(dev, mii_reg); + udelay(MII_DELAY); + smc_set_mii(dev, mii_reg | MII_MCLK); + udelay(MII_DELAY); + } +} + +static unsigned int smc_mii_in(struct net_device *dev, int bits) +{ + unsigned int mii_reg, mask, val; + + mii_reg = smc_get_mii(dev) & ~(MII_MCLK | MII_MDOE | MII_MDO); + smc_set_mii(dev, mii_reg); + + for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { + if (smc_get_mii(dev) & MII_MDI) + val |= mask; + + smc_set_mii(dev, mii_reg); + udelay(MII_DELAY); + smc_set_mii(dev, mii_reg | MII_MCLK); + udelay(MII_DELAY); + } + + return val; +} + +/* + * Reads a register from the MII Management serial interface + */ +static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) +{ + unsigned int phydata, old_bank; + + /* Save the current bank, and select bank 3 */ + old_bank = smc_current_bank(dev); + smc_select_bank(dev, 3); + + /* Idle - 32 ones */ + smc_mii_out(dev, 0xffffffff, 32); + + /* Start code (01) + read (10) + phyaddr + phyreg */ + smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); + + /* Turnaround (2bits) + phydata */ + phydata = smc_mii_in(dev, 18); + + /* Return to idle state */ + smc_set_mii(dev, smc_get_mii(dev) & ~(MII_MCLK|MII_MDOE|MII_MDO)); + + /* And select original bank */ + smc_select_bank(dev, old_bank); + + DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", + __FUNCTION__, phyaddr, phyreg, phydata); + + return phydata; +} + +/* + * Writes a register to the MII Management serial interface + */ +static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, + int phydata) +{ + unsigned int old_bank; + + /* Save the current bank, and select bank 3 */ + old_bank = smc_current_bank(dev); + smc_select_bank(dev, 3); + + /* Idle - 32 ones */ + smc_mii_out(dev, 0xffffffff, 32); + + /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ + smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); + + /* Return to idle state */ + smc_set_mii(dev, smc_get_mii(dev) & ~(MII_MCLK|MII_MDOE|MII_MDO)); + + /* And select original bank */ + smc_select_bank(dev, old_bank); + + DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", + __FUNCTION__, phyaddr, phyreg, phydata); +} + +/* + * Finds and reports the PHY address + */ +static void smc_detect_phy(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + int phyaddr; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + lp->phy_type = 0; + + /* + * Scan all 32 PHY addresses if necessary, starting at + * PHY#1 to PHY#31, and then PHY#0 last. + */ + for (phyaddr = 1; phyaddr < 33; ++phyaddr) { + unsigned int id1, id2; + + /* Read the PHY identifiers */ + id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); + id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); + + DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n", + dev->name, id1, id2); + + /* Make sure it is a valid identifier */ + if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && + id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { + /* Save the PHY's address */ + lp->mii.phy_id = phyaddr & 31; + lp->phy_type = id1 << 16 | id2; + break; + } + } +} + +/* + * Sets the PHY to a configuration as determined by the user + */ +static int smc_phy_fixed(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + int phyaddr = lp->mii.phy_id; + int bmcr, cfg1; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + /* Enter Link Disable state */ + cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); + cfg1 |= PHY_CFG1_LNKDIS; + smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); + + /* + * Set our fixed capabilities + * Disable auto-negotiation + */ + bmcr = 0; + + if (lp->ctl_rfduplx) + bmcr |= BMCR_FULLDPLX; + + if (lp->ctl_rspeed == 100) + bmcr |= BMCR_SPEED100; + + /* Write our capabilities to the phy control register */ + smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); + + /* Re-Configure the Receive/Phy Control register */ + smc_set_rpc(dev, lp->rpc_cur_mode); + + return 1; +} + +/* + * smc_phy_reset - reset the phy + * @dev: net device + * @phy: phy address + * + * Issue a software reset for the specified PHY and + * wait up to 100ms for the reset to complete. We should + * not access the PHY for 50ms after issuing the reset. + * + * The time to wait appears to be dependent on the PHY. + * + * Must be called with lp->lock locked. + */ +static int smc_phy_reset(struct net_device *dev, int phy) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned int bmcr; + int timeout; + + smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); + + for (timeout = 2; timeout; timeout--) { + spin_unlock_irq(&lp->lock); + msleep(50); + spin_lock_irq(&lp->lock); + + bmcr = smc_phy_read(dev, phy, MII_BMCR); + if (!(bmcr & BMCR_RESET)) + break; + } + + return bmcr & BMCR_RESET; +} + +/* + * smc_phy_powerdown - powerdown phy + * @dev: net device + * @phy: phy address + * + * Power down the specified PHY + */ +static void smc_phy_powerdown(struct net_device *dev, int phy) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned int bmcr; + + spin_lock_irq(&lp->lock); + bmcr = smc_phy_read(dev, phy, MII_BMCR); + smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); + spin_unlock_irq(&lp->lock); +} + +/* + * smc_phy_check_media - check the media status and adjust TCR + * @dev: net device + * @init: set true for initialisation + * + * Select duplex mode depending on negotiation state. This + * also updates our carrier state. + */ +static void smc_phy_check_media(struct net_device *dev, int init) +{ + struct smc_local *lp = netdev_priv(dev); + + if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { + unsigned int old_bank; + + /* duplex state has changed */ + if (lp->mii.full_duplex) { + lp->tcr_cur_mode |= TCR_SWFDUP; + } else { + lp->tcr_cur_mode &= ~TCR_SWFDUP; + } + + old_bank = smc_current_bank(dev); + smc_select_bank(dev, 0); + smc_set_tcr(dev, lp->tcr_cur_mode); + smc_select_bank(dev, old_bank); + } +} + +/* + * Configures the specified PHY through the MII management interface + * using Autonegotiation. + * Calls smc_phy_fixed() if the user has requested a certain config. + * If RPC ANEG bit is set, the media selection is dependent purely on + * the selection by the MII (either in the MII BMCR reg or the result + * of autonegotiation.) If the RPC ANEG bit is cleared, the selection + * is controlled by the RPC SPEED and RPC DPLX bits. + */ +static void smc_phy_configure(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + int phyaddr = lp->mii.phy_id; + int my_phy_caps; /* My PHY capabilities */ + int my_ad_caps; /* My Advertised capabilities */ + int status; + + DBG(3, "%s:smc_program_phy()\n", dev->name); + + spin_lock_irq(&lp->lock); + + /* + * We should not be called if phy_type is zero. + */ + if (lp->phy_type == 0) + goto smc_phy_configure_exit; + + if (smc_phy_reset(dev, phyaddr)) { + printk("%s: PHY reset timed out\n", dev->name); + goto smc_phy_configure_exit; + } + + /* + * Enable PHY Interrupts (for register 18) + * Interrupts listed here are disabled + */ + smc_phy_write(dev, phyaddr, PHY_MASK_REG, + PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | + PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | + PHY_INT_SPDDET | PHY_INT_DPLXDET); + + /* Configure the Receive/Phy Control register */ + smc_select_bank(dev, 0); + smc_set_rpc(dev, lp->rpc_cur_mode); + + /* If the user requested no auto neg, then go set his request */ + if (lp->mii.force_media) { + smc_phy_fixed(dev); + goto smc_phy_configure_exit; + } + + /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ + my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); + + if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { + printk(KERN_INFO "Auto negotiation NOT supported\n"); + smc_phy_fixed(dev); + goto smc_phy_configure_exit; + } + + my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ + + if (my_phy_caps & BMSR_100BASE4) + my_ad_caps |= ADVERTISE_100BASE4; + if (my_phy_caps & BMSR_100FULL) + my_ad_caps |= ADVERTISE_100FULL; + if (my_phy_caps & BMSR_100HALF) + my_ad_caps |= ADVERTISE_100HALF; + if (my_phy_caps & BMSR_10FULL) + my_ad_caps |= ADVERTISE_10FULL; + if (my_phy_caps & BMSR_10HALF) + my_ad_caps |= ADVERTISE_10HALF; + + /* Disable capabilities not selected by our user */ + if (lp->ctl_rspeed != 100) + my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); + + if (!lp->ctl_rfduplx) + my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); + + /* Update our Auto-Neg Advertisement Register */ + smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); + lp->mii.advertising = my_ad_caps; + + /* + * Read the register back. Without this, it appears that when + * auto-negotiation is restarted, sometimes it isn't ready and + * the link does not come up. + */ + status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); + + DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps); + DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps); + + /* Restart auto-negotiation process in order to advertise my caps */ + smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); + + smc_phy_check_media(dev, 1); + +smc_phy_configure_exit: + spin_unlock_irq(&lp->lock); +} + +/* + * smc_phy_interrupt + * + * Purpose: Handle interrupts relating to PHY register 18. This is + * called from the "hard" interrupt handler under our private spinlock. + */ +static void smc_phy_interrupt(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + int phyaddr = lp->mii.phy_id; + int phy18; + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + if (lp->phy_type == 0) + return; + + for(;;) { + smc_phy_check_media(dev, 0); + + /* Read PHY Register 18, Status Output */ + phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); + if ((phy18 & PHY_INT_INT) == 0) + break; + } +} + +/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ + +static void smc_10bt_check_media(struct net_device *dev, int init) +{ + struct smc_local *lp = netdev_priv(dev); + u16 old_carrier, new_carrier, old_bank; + + old_bank = smc_current_bank(dev); + smc_select_bank(dev, 0); + old_carrier = netif_carrier_ok(dev) ? 1 : 0; + new_carrier = smc_es_link_ok (dev); + + if (init || (old_carrier != new_carrier)) { + if (!new_carrier) { + netif_carrier_off(dev); + } else { + netif_carrier_on(dev); + } + if (netif_msg_link(lp)) + printk(KERN_INFO "%s: link %s\n", dev->name, + new_carrier ? "up" : "down"); + } + smc_select_bank(dev, old_bank); +} + +static void smc_eph_interrupt(struct net_device *dev) +{ + + unsigned int old_bank, ctl; + + smc_10bt_check_media(dev, 0); + + old_bank = smc_current_bank(dev); smc_select_bank(dev, 1); + + ctl = smc_get_ctl(dev); + smc_set_ctl(dev, ctl & ~CTL_LE_ENABLE); + smc_set_ctl(dev, ctl); + + smc_select_bank(dev, old_bank); +} + +/* + * This is the main routine of the driver, to handle the device when + * it needs some attention. + */ +static irqreturn_t smc_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct net_device *dev = dev_id; + + struct smc_local *lp = netdev_priv(dev); + int status, mask, timeout, card_stats; + int saved_bank, saved_pointer; + + DBG(3, "%s: %s\n", dev->name, __FUNCTION__); + + saved_bank = smc_current_bank(dev); + smc_select_bank(dev, 2); + saved_pointer = smc_get_ptr(dev); + mask = smc_get_int_mask(dev); + smc_set_int_mask(dev, 0); + + /* set a timeout value, so I don't stay here forever */ + timeout = 8; + + do { + status = smc_get_int(dev); + + DBG(2, "%s: STATUS:%s%s%s%s%s%s%s%s MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", + dev->name, + (status&(IM_RCV_INT))?" RCV":"", + (status&(IM_TX_INT))?" TX":"", + (status&(IM_TX_EMPTY_INT))?" TX_EMPTY":"", + (status&(1<<3))?" ALLOC":"", + (status&(IM_RX_OVRN_INT))?" RXOVER":"", + (status&(IM_EPH_INT))?" EPH":"", + (status&(IM_ERCV_INT))?" ERCV":"", + (status&(IM_MDINT))?" MD":"", + mask, + ({ int meminfo; smc_select_bank(dev, 0); + meminfo = smc_get_mir(dev); + smc_select_bank(dev, 2); meminfo; }), + smc_get_fifo(dev)); + + status &= mask; + if (!status) + break; + + spin_lock(&lp->lock); + + if (status & IM_RCV_INT) { + DBG(3, "%s: RX irq\n", dev->name); + smc_rcv(dev); + } else if (status & IM_TX_INT) { + DBG(3, "%s: TX int\n", dev->name); + smc_tx(dev); + smc_ack_int(dev, IM_TX_INT); +#if THROTTLE_TX_PKTS + netif_wake_queue(dev); +#endif + } else if (status & IM_ALLOC_INT) { + DBG(3, "%s: Allocation irq\n", dev->name); + smc_hardware_send_packet(dev); + mask |= (IM_TX_INT | IM_TX_EMPTY_INT); + mask &= ~IM_ALLOC_INT; +#if ! THROTTLE_TX_PKTS + netif_wake_queue(dev); +#endif + } else if (status & IM_TX_EMPTY_INT) { + DBG(3, "%s: TX empty\n", dev->name); + mask &= ~IM_TX_EMPTY_INT; + + /* update stats */ + smc_select_bank(dev, 0); + card_stats = smc_get_counter(dev); + smc_select_bank(dev, 2); + + /* single collisions */ + lp->stats.collisions += card_stats & 0xF; + card_stats >>= 4; + + /* multiple collisions */ + lp->stats.collisions += card_stats & 0xF; + } else if (status & IM_RX_OVRN_INT) { + DBG(1, "%s: RX overrun\n", dev->name); + smc_ack_int(dev, IM_RX_OVRN_INT); + lp->stats.rx_errors++; + lp->stats.rx_fifo_errors++; + } else if (status & IM_EPH_INT) { + smc_eph_interrupt(dev); + } else if (status & IM_MDINT) { + smc_ack_int(dev, IM_MDINT); + smc_phy_interrupt(dev); + } else if (status & IM_ERCV_INT) { + smc_ack_int(dev, IM_ERCV_INT); + PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name); + } + + spin_unlock(&lp->lock); + } while (--timeout); + + /* restore register states */ + smc_set_int_mask(dev, mask); + smc_set_ptr(dev, saved_pointer); + smc_select_bank(dev, saved_bank); + + DBG(3, "%s: Interrupt done (%d loops)\n", dev->name, 8-timeout); + + /* + * We return IRQ_HANDLED unconditionally here even if there was + * nothing to do. There is a possibility that a packet might + * get enqueued into the chip right after TX_EMPTY_INT is raised + * but just before the CPU acknowledges the IRQ. + * Better take an unneeded IRQ in some occasions than complexifying + * the code for all cases. + */ + return IRQ_HANDLED; +} + +/* Our watchdog timed out. Called by the networking layer */ +static void smc_timeout(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + smc_reset(dev); + smc_enable(dev); + +#if 0 + /* + * Reconfiguring the PHY doesn't seem like a bad idea here, but + * it introduced a problem. Now that this is a timeout routine, + * we are getting called from within an interrupt context. + * smc_phy_configure() calls msleep() which calls + * schedule_timeout() which calls schedule(). When schedule() + * is called from an interrupt context, it prints out + * "Scheduling in interrupt" and then calls BUG(). This is + * obviously not desirable. This was worked around by removing + * the call to smc_phy_configure() here because it didn't seem + * absolutely necessary. Ultimately, if msleep() is + * supposed to be usable from an interrupt context (which it + * looks like it thinks it should handle), it should be fixed. + */ + if (lp->phy_type != 0) + smc_phy_configure(dev); +#endif + + /* clear anything saved */ + if (lp->saved_skb != NULL) { + dev_kfree_skb (lp->saved_skb); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_aborted_errors++; + } + /* We can accept TX packets again */ + dev->trans_start = jiffies; + netif_wake_queue(dev); +} + +/* + * This sets the internal hardware table to filter out unwanted multicast + * packets before they take up memory. + * + * The SMC chip uses a hash table where the high 6 bits of the CRC of + * address are the offset into the table. If that bit is 1, then the + * multicast packet is accepted. Otherwise, it's dropped silently. + * + * To use the 6 bits as an offset into the table, the high 3 bits are the + * number of the 8 bit register, while the low 3 bits are the bit within + * that register. + * + * This routine is based very heavily on the one provided by Peter Cammaert. + */ +static void +smc_setmulticast(struct net_device *dev) +{ + int i; + int count; + u8 multicast_table[8]; + struct dev_mc_list *cur_addr, *addrs; + + /* table for flipping the order of 3 bits */ + static unsigned char invert3[] = { 0, 4, 2, 6, 1, 5, 3, 7 }; + + if (!dev) return; + count = dev->mc_count; + addrs = dev->mc_list; + + /* start with a table of all zeros: reject all */ + memset(multicast_table, 0, sizeof(multicast_table)); + + cur_addr = addrs; + for (i = 0; i < count; i++, cur_addr = cur_addr->next) { + int position; + + /* do we have a pointer here? */ + if (!cur_addr) + break; + /* make sure this is a multicast address - shouldn't this + be a given if we have it here ? */ + if (!(*cur_addr->dmi_addr & 1)) + continue; + + /* only use the low order bits */ + position = crc32_le(~0, cur_addr->dmi_addr, 6) & 0x3f; + + /* do some messy swapping to put the bit in the right spot */ + multicast_table[invert3[position&7]] |= + (1<>3)&7]); + + } + /* now, the table can be loaded into the chipset */ + smc_select_bank(dev, 3); + smc_set_mcast(dev, multicast_table); +} + +/* + * This routine will, depending on the values passed to it, + * either make it accept multicast packets, go into + * promiscuous mode (for TCPDUMP and cousins) or accept + * a select set of multicast packets + */ +static void smc_set_multicast_list(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + smc_select_bank(dev, 0); + if (dev->flags & IFF_PROMISC) { + DBG(2, "%s: RCR_PRMS\n", dev->name); + lp->rcr_cur_mode |= RCR_PRMS; + smc_set_rcr(dev, lp->rcr_cur_mode); + } + +/* BUG? I never disable promiscuous mode if multicasting was turned on. + Now, I turn off promiscuous mode, but I don't do anything to multicasting + when promiscuous mode is turned on. +*/ + + /* + * Here, I am setting this to accept all multicast packets. + * I don't need to zero the multicast table, because the flag is + * checked before the table is + */ + else if (dev->flags & IFF_ALLMULTI || dev->mc_count > 16) { + lp->rcr_cur_mode |= RCR_ALMUL; + smc_set_rcr(dev, lp->rcr_cur_mode); + DBG(2, "%s: RCR_ALMUL\n", dev->name); + } + + /* + * We just get all multicast packets even if we only want them + * from one source. This will be changed at some future point. + */ + else if (dev->mc_count) { + /* support hardware multicasting */ + + /* be sure I get rid of flags I might have set */ + lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); + smc_set_rcr(dev, lp->rcr_cur_mode); + /* + * NOTE: this has to set the bank, so make sure it is the + * last thing called. The bank is set to zero at the top + */ + smc_setmulticast(dev); + } else { + DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name); + lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); + smc_set_rcr(dev, lp->rcr_cur_mode); + + /* + * since I'm disabling all multicast entirely, I need to + * clear the multicast list + */ + smc_select_bank(dev, 3); + smc_clear_mcast(dev); + } +} + + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc.. + */ +static int +smc_open(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + /* + * Check that the address is valid. If its not, refuse + * to bring the device up. The user must specify an + * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx + */ + if (!is_valid_ether_addr(dev->dev_addr)) { + DBG(2, "smc_open: no valid ethernet hw addr\n"); + return -EINVAL; + } + + /* clear out all the junk that was put here before... */ + lp->saved_skb = NULL; + + /* Setup the default Register Modes */ + lp->tcr_cur_mode = TCR_DEFAULT; + lp->rcr_cur_mode = RCR_DEFAULT; + lp->rpc_cur_mode = RPC_DEFAULT; + + /* + * If we are not using a MII interface, we need to + * monitor our own carrier signal to detect faults. + */ + if (lp->phy_type == 0) + lp->tcr_cur_mode |= TCR_MON_CSN; + + /* reset the hardware */ + smc_reset(dev); + smc_enable(dev); + + smc_select_bank(dev, 1); + smc_set_mac_addr(dev); + + /* Configure the PHY */ + if (lp->phy_type != 0) + smc_phy_configure(dev); + else { + spin_lock_irq(&lp->lock); + smc_10bt_check_media(dev, 1); + spin_unlock_irq(&lp->lock); + } + + /* + * make sure to initialize the link state with netif_carrier_off() + * somewhere, too --jgarzik + * + * smc_phy_configure() and smc_10bt_check_media() does that. --rmk + */ + netif_start_queue(dev); + return 0; +} + +/* + * smc_close + * + * this makes the board clean up everything that it can + * and not talk to the outside world. Caused by + * an 'ifconfig ethX down' + */ +static int smc_close(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + netif_stop_queue(dev); + netif_carrier_off(dev); + + /* clear everything */ + smc_shutdown(dev); + + if (lp->phy_type != 0) + smc_phy_powerdown(dev, lp->mii.phy_id); + + return 0; +} + +/* + * Get the current statistics. + * This may be called with the card open or closed. + */ +static struct net_device_stats *smc_query_statistics(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + DBG(2, "%s: %s\n", dev->name, __FUNCTION__); + + return &lp->stats; +} + +/* + * Ethtool support + */ +static int +smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct smc_local *lp = netdev_priv(dev); + int ret; + + cmd->maxtxpkt = 1; + cmd->maxrxpkt = 1; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_ethtool_gset(&lp->mii, cmd); + spin_unlock_irq(&lp->lock); + } else { + cmd->supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_TP | SUPPORTED_AUI; + + if (lp->ctl_rspeed == 10) + cmd->speed = SPEED_10; + else if (lp->ctl_rspeed == 100) + cmd->speed = SPEED_100; + + cmd->autoneg = AUTONEG_DISABLE; + cmd->transceiver = XCVR_INTERNAL; + cmd->port = 0; + cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF; + + ret = 0; + } + + return ret; +} + +static int +smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct smc_local *lp = netdev_priv(dev); + int ret; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_ethtool_sset(&lp->mii, cmd); + spin_unlock_irq(&lp->lock); + } else { + if (cmd->autoneg != AUTONEG_DISABLE || + cmd->speed != SPEED_10 || + (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) || + (cmd->port != PORT_TP && cmd->port != PORT_AUI)) + return -EINVAL; + +// lp->port = cmd->port; + lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL; + +// if (netif_running(dev)) +// smc_set_port(dev); + + ret = 0; + } + + return ret; +} + +static void +smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) +{ + strncpy(info->driver, CARDNAME, sizeof(info->driver)); + strncpy(info->version, version, sizeof(info->version)); + strncpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info)); +} + +static int smc_ethtool_nwayreset(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + int ret = -EINVAL; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_nway_restart(&lp->mii); + spin_unlock_irq(&lp->lock); + } + + return ret; +} + +static u32 smc_ethtool_getmsglevel(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return lp->msg_enable; +} + +static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) +{ + struct smc_local *lp = netdev_priv(dev); + lp->msg_enable = level; +} + +static struct ethtool_ops smc_ethtool_ops = { + .get_settings = smc_ethtool_getsettings, + .set_settings = smc_ethtool_setsettings, + .get_drvinfo = smc_ethtool_getdrvinfo, + + .get_msglevel = smc_ethtool_getmsglevel, + .set_msglevel = smc_ethtool_setmsglevel, + .nway_reset = smc_ethtool_nwayreset, + .get_link = ethtool_op_get_link, +// .get_eeprom = smc_ethtool_geteeprom, +// .set_eeprom = smc_ethtool_seteeprom, +}; + +/* + * smc_findirq + * + * This routine has a simple purpose -- make the SMC chip generate an + * interrupt, so an auto-detect routine can detect it, and find the IRQ, + */ +/* + * does this still work? + * + * I just deleted auto_irq.c, since it was never built... + * --jgarzik + */ +static int __init smc_findirq(struct net_device *dev) +{ + int timeout = 20; + unsigned long cookie; + + DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__); + + cookie = probe_irq_on(); + + /* + * What I try to do here is trigger an ALLOC_INT. This is done + * by allocating a small chunk of memory, which will give an interrupt + * when done. + */ + /* enable ALLOCation interrupts ONLY */ + smc_select_bank(dev, 2); + smc_set_int_mask(dev, IM_ALLOC_INT); + + /* + * Allocate 512 bytes of memory. Note that the chip was just + * reset so all the memory is available + */ + smc_set_mmu_cmd(dev, MC_ALLOC | 1); + + /* + * Wait until positive that the interrupt has been generated + */ + do { + int int_status; + udelay(10); + int_status = smc_get_int(dev); + if (int_status & IM_ALLOC_INT) + break; /* got the interrupt */ + } while (--timeout); + + /* + * there is really nothing that I can do here if timeout fails, + * as autoirq_report will return a 0 anyway, which is what I + * want in this case. Plus, the clean up is needed in both + * cases. + */ + + /* and disable all interrupts again */ + smc_set_int_mask(dev, 0); + + /* and return what I found */ + return probe_irq_off(cookie); +} + +/* + * Function: smc_probe(unsigned long ioaddr) + * + * Purpose: + * Tests to see if a given ioaddr points to an SMC91x chip. + * Returns a 0 on success + * + * Algorithm: + * (1) see if the high byte of BANK_SELECT is 0x33 + * (2) compare the ioaddr with the base register's address + * (3) see if I recognize the chip ID in the appropriate register + * + * Here I do typical initialization tasks. + * + * o Initialize the structure if needed + * o print out my vanity message if not done so already + * o print out what type of hardware is detected + * o print out the ethernet address + * o find the IRQ + * o set up my private data + * o configure the dev structure with my subroutines + * o actually GRAB the irq. + * o GRAB the region + */ +static int __init smc_setup(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + static int version_printed = 0; + int i, retval; + unsigned int val, revision_register; + const char *version_string; + + DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__); + + /* + * The above MIGHT indicate a device, but I need to write to + * further test this. + */ + smc_select_bank(dev, 0); + val = smc_current_bank(dev); + if ((val & 0xFF00) != 0x3300) { + retval = -ENODEV; + goto err_out; + } + + /* + * well, we've already written once, so hopefully another + * time won't hurt. This time, I need to switch the bank + * register to bank 1, so I can access the base address + * register + */ + + smc_select_bank(dev, 1); + val = smc_get_base(dev); + val = ((val & 0x1F00) >> 3) << lp->addrshift; + if ((lp->physaddr & ((PAGE_SIZE-1)<addrshift)) != val) { + printk("%s: IOADDR 0x%08x doesn't match configuration (%x).\n", + CARDNAME, lp->physaddr, val); + } + + /* + * check if the revision register is something that I + * recognize. These might need to be added to later, + * as future revisions could be added. + */ + smc_select_bank(dev, 3); + revision_register = smc_get_rev(dev); + DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register); + version_string = chip_ids[ (revision_register >> 4) & 0xF]; + if (!version_string || (revision_register & 0xff00) != 0x3300) { + /* I don't recognize this chip, so... */ + printk("%s: IO 0x%08x: Unrecognized revision register 0x%04x" + ", Contact author.\n", CARDNAME, + lp->ioaddr, revision_register); + + retval = -ENODEV; + goto err_out; + } + + /* At this point I'll assume that the chip is an SMC91x. */ + if (version_printed++ == 0) + printk("%s", version); + + /* fill in some of the fields */ + dev->base_addr = lp->ioaddr; + lp->version = revision_register & 0xff; + + /* Get the MAC address */ + smc_select_bank(dev, 1); + smc_get_mac_addr(dev); + + /* now, reset the chip, and put it into a known state */ + smc_reset(dev); + + /* + * If dev->irq is 0, then the device has to be banged on to see + * what the IRQ is. + * + * This banging doesn't always detect the IRQ, for unknown reasons. + * a workaround is to reset the chip and try again. + * + * Interestingly, the DOS packet driver *SETS* the IRQ on the card to + * be what is requested on the command line. I don't do that, mostly + * because the card that I have uses a non-standard method of accessing + * the IRQs, and because this _should_ work in most configurations. + * + * Specifying an IRQ is done with the assumption that the user knows + * what (s)he is doing. No checking is done!!!! + */ + if (dev->irq < 1) { + int trials; + + trials = 3; + while (trials--) { + dev->irq = smc_findirq(dev); + if (dev->irq) + break; + /* kick the card and try again */ + smc_reset(dev); + } + } + if (dev->irq == 0) { + printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n", + dev->name); + retval = -ENODEV; + goto err_out; + } + dev->irq = irq_canonicalize(dev->irq); + + /* Fill in the fields of the device structure with ethernet values. */ + ether_setup(dev); + + dev->open = smc_open; + dev->stop = smc_close; + dev->hard_start_xmit = smc_hard_start_xmit; + dev->tx_timeout = smc_timeout; + dev->watchdog_timeo = msecs_to_jiffies(watchdog); + dev->get_stats = smc_query_statistics; + dev->set_multicast_list = smc_set_multicast_list; + dev->ethtool_ops = &smc_ethtool_ops; + + spin_lock_init(&lp->lock); + lp->mii.phy_id_mask = 0x1f; + lp->mii.reg_num_mask = 0x1f; + lp->mii.force_media = 0; + lp->mii.full_duplex = 0; + lp->mii.dev = dev; + lp->mii.mdio_read = smc_phy_read; + lp->mii.mdio_write = smc_phy_write; + + /* + * Locate the phy, if any. + */ + if (lp->version >= (CHIP_91100 << 4)) + smc_detect_phy(dev); + + /* Set default parameters */ + lp->msg_enable = NETIF_MSG_LINK; + lp->ctl_rfduplx = 0; + lp->ctl_rspeed = 10; + + if (lp->version >= (CHIP_91100 << 4)) { + lp->ctl_rfduplx = 1; + lp->ctl_rspeed = 100; + } + + /* Grab the IRQ */ + retval = request_irq(dev->irq, &smc_interrupt, 0, dev->name, dev); + if (retval) + goto err_out; + +#ifdef SMC_USE_PXA_DMA + { + int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW, + smc_pxa_dma_irq, NULL); + if (dma >= 0) + dev->dma = dma; + } +#endif + + retval = register_netdev(dev); + if (retval == 0) { + /* now, print out the card info, in a short format.. */ + printk("%s: %s (rev %d) at %#08x IRQ %d", + dev->name, version_string, revision_register & 0x0f, + lp->physaddr, dev->irq); + + if (dev->dma != (unsigned char)-1) + printk(" DMA %d", dev->dma); + + printk("%s%s\n", nowait ? " [nowait]" : "", + THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); + + if (!is_valid_ether_addr(dev->dev_addr)) { + printk("%s: Invalid ethernet MAC address. Please " + "set using ifconfig\n", dev->name); + } else { + /* Print the Ethernet address */ + printk("%s: Ethernet addr: ", dev->name); + for (i = 0; i < 5; i++) + printk("%2.2x:", dev->dev_addr[i]); + printk("%2.2x\n", dev->dev_addr[5]); + } + + if (lp->phy_type == 0) { + PRINTK("%s: No PHY found\n", dev->name); + } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { + PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name); + } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { + PRINTK("%s: PHY LAN83C180\n", dev->name); + } + } + +err_out: +#ifdef SMC_USE_PXA_DMA + if (retval && dev->dma != (unsigned char)-1) + pxa_free_dma(dev->dma); +#endif + return retval; +} + +/* FIXME: SMC 91C96 has attribute space... */ +#if 0 +static int smc_enable_device(unsigned long attrib_phys) +{ + unsigned long flags; + unsigned char ecor, ecsr; + void *addr; + + /* + * Map the attribute space. This is overkill, but clean. + */ + addr = ioremap(attrib_phys, ATTRIB_SIZE); + if (!addr) + return -ENOMEM; + + /* + * Reset the device. We must disable IRQs around this + * since a reset causes the IRQ line become active. + */ + local_irq_save(flags); + ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; + writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); + readb(addr + (ECOR << SMC_IO_SHIFT)); + + /* + * Wait 100us for the chip to reset. + */ + udelay(100); + + /* + * The device will ignore all writes to the enable bit while + * reset is asserted, even if the reset bit is cleared in the + * same write. Must clear reset first, then enable the device. + */ + writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); + writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); + + /* + * Set the appropriate byte/word mode. + */ + ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; +#ifndef SMC_CAN_USE_16BIT + ecsr |= ECSR_IOIS8; +#endif + writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); + local_irq_restore(flags); + + iounmap(addr); + + /* + * Wait for the chip to wake up. We could poll the control + * register in the main register space, but that isn't mapped + * yet. We know this is going to take 750us. + */ + msleep(1); + + return 0; +} +#endif + +/* + * smc_init(void) + * Input parameters: + * dev->base_addr == 0, try to find all possible locations + * dev->base_addr > 0x1ff, this is the address to check + * dev->base_addr == , return failure code + * + * Output: + * 0 --> there is a device + * anything else, error + */ +static int smc_drv_probe(struct device *dev) +{ + struct net_device *ndev; + struct resource *res = NULL; + struct smc_local *lp; + int ret = -ENODEV; + u32 *addr, addrshift, val; + struct platform_device *pdev = to_platform_device(dev); + + DBG (2, "trying to probe SMC91x...\n"); + if (!pdev || strncmp (pdev->name, "smc91x", 6)) return ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + { + printk("%s: no mem resource defined.\n", CARDNAME); + goto out; + } + + /* + * Request the regions. + */ + if (!request_mem_region(res->start, res->end - res->start, + "smc91x")) { + printk("%s: device busy.\n", CARDNAME); + ret = -EBUSY; + goto out; + } + + addr = ioremap(res->start, res->end - res->start); + if (!addr) + { + printk("%s: ioremap failed.\n", CARDNAME); + ret = -ENOMEM; + goto out; + } + /* FIXME: make configurable */ + addrshift = 0; + + /* First, see if the high byte is 0x33 */ + val = readw(((u32) addr) + (SMC_REG_BANK_SELECT<start); + } + printk("%s: probe failed\n", CARDNAME); + ret = -ENODEV; + goto out; + } + + ndev = alloc_etherdev(sizeof(struct smc_local)); + if (!ndev) { + printk("%s: could not allocate device.\n", CARDNAME); + goto release; + } + SET_MODULE_OWNER(ndev); + SET_NETDEV_DEV(ndev, dev); + + lp = netdev_priv(ndev); + lp->physaddr = res->start; + lp->ioaddr = (u32) addr; + lp->addrshift = addrshift; + + if (res->flags & IORESOURCE_MEM_16BIT) + lp->iomode = SMC_IO_CAN_16BIT; + else + lp->iomode = SMC_IO_CAN_32BIT; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res->start) + { + printk("%s: IRQ not defined.\n", CARDNAME); + goto free_ndev; + } + + ndev->irq = res->start; + ndev->dma = -1; + + if (res->flags & IORESOURCE_IRQ_HIGHEDGE) + set_irq_type(ndev->irq, IRQT_RISING); + if (res->flags & IORESOURCE_IRQ_LOWEDGE) + set_irq_type(ndev->irq, IRQT_FALLING); + + dev_set_drvdata(dev, ndev); + ret = smc_setup(ndev); + if (ret != 0) { + printk("%s: setup failed.\n", CARDNAME); + goto free_ndev; + } +out: + return ret; +free_ndev: + dev_set_drvdata(dev, NULL); + kfree (ndev); +release: + release_mem_region(res->start, res->end - res->start); + goto out; +} + +static int smc_drv_remove(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev = dev_get_drvdata(dev); + struct resource *res; + + dev_set_drvdata(dev, NULL); + + unregister_netdev(ndev); + + free_irq(ndev->irq, ndev); + + if (ndev->dma != (unsigned char) -1) + { +#ifdef SMC_USE_PXA_DMA + pxa_free_dma(ndev->dma); +#else + printk ("how to free DMA???"); +#endif + } + + iounmap((void *)ndev->base_addr); + /* FIXME: SMC 91C96 */ +#if 0 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) + release_mem_region(res->start, ATTRIB_SIZE); +#endif + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start); + + free_netdev(ndev); + + return 0; +} + +static int smc_drv_suspend(struct device *dev, u32 state, u32 level) +{ + struct net_device *ndev = dev_get_drvdata(dev); + + if (ndev && level == SUSPEND_DISABLE) { + if (netif_running(ndev)) { + netif_device_detach(ndev); + smc_shutdown(ndev); + } + } + return 0; +} + +static int smc_drv_resume(struct device *dev, u32 level) +{ +// struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev = dev_get_drvdata(dev); + + if (ndev && level == RESUME_ENABLE) { + struct smc_local *lp = netdev_priv(ndev); +// SMC 91C96 +// if (pdev->num_resources == 3) +// smc_enable_device(pdev->resource[2].start); + if (netif_running(ndev)) { + smc_reset(ndev); + smc_enable(ndev); + smc_select_bank(ndev, 1); + smc_set_mac_addr(ndev); + if (lp->phy_type != 0) + smc_phy_configure(ndev); + netif_device_attach(ndev); + } + } + return 0; +} + +static struct device_driver smc_driver = { + .name = CARDNAME, + .bus = &platform_bus_type, + .probe = smc_drv_probe, + .remove = smc_drv_remove, + .suspend = smc_drv_suspend, + .resume = smc_drv_resume, +}; + +static int __init smc_init(void) +{ +#ifdef MODULE + if (io == -1) + printk(KERN_WARNING + "%s: You shouldn't use auto-probing with insmod!\n", + CARDNAME); +#endif + + return driver_register(&smc_driver); +} + +static void __exit smc_cleanup(void) +{ + driver_unregister(&smc_driver); +} + +module_init(smc_init); +module_exit(smc_cleanup); diff -x .svn -urN linux-2.6.8-rc2/drivers/net/smc91x-new-hal.h linux-2.6.8-rc2-pnp1/drivers/net/smc91x-new-hal.h --- linux-2.6.8-rc2/drivers/net/smc91x-new-hal.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/smc91x-new-hal.h 2004-07-27 14:01:19.000000000 +0200 @@ -0,0 +1,1315 @@ +/*------------------------------------------------------------------------ + . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. + . + . Copyright (C) 1996 by Erik Stahlman + . Copyright (C) 2001 Standard Microsystems Corporation + . Developed by Simple Network Magic Corporation + . Copyright (C) 2003 Monta Vista Software, Inc. + . Unified SMC91x driver by Nicolas Pitre + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . Authors + . Erik Stahlman + . Daris A Nevil + . Nicolas Pitre + . + ---------------------------------------------------------------------------*/ +#ifndef _SMC91X_H_ +#define _SMC91X_H_ + +#include + +#define SMC_IO_CAN_8BIT (1<<0) +#define SMC_IO_CAN_16BIT (1<<1) +#define SMC_IO_CAN_32BIT (1<<2) + +struct smc_local { + + struct sk_buff *saved_skb; /* store packet while no memory */ + struct net_device_stats stats; /* kernel statistics FIXME: generic? */ + int version; /* chip revision */ + int tcr_cur_mode; /* current active transm. mode */ + int rcr_cur_mode; /* current active receive mode */ + int rpc_cur_mode; /* active receive/phy mode */ + int ctl_rfduplx; + int ctl_rspeed; + u32 msg_enable; + u32 phy_type; + struct mii_if_info mii; + spinlock_t lock; /* FIXME: generic? */ + u32 physaddr; + u32 ioaddr; /* virtual address */ + u8 iomode; /* SMC_IO_CAN__... */ + u8 addrshift; /* in case of flaky hardware */ + +}; + + +/* ------------------------------------------------------------------------ */ +/* Obsolete old stuff - to be replaced... */ +/* ------------------------------------------------------------------------ */ +#if 0 +/* + * Define your architecture specific bus configuration parameters here. + */ + +#if defined(CONFIG_SA1100_GRAPHICSCLIENT) || \ + defined(CONFIG_SA1100_PFS168) || \ + defined(CONFIG_SA1100_FLEXANET) || \ + defined(CONFIG_SA1100_GRAPHICSMASTER) || \ + defined(CONFIG_ARCH_LUBBOCK) + +/* We can only do 16-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +/* The first two address lines aren't connected... */ +#define SMC_IO_SHIFT 2 + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) + +#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) + +/* We can only do 16-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +#define SMC_IO_SHIFT 0 + +#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) +#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) +#define SMC_insw(a, r, p, l) \ + do { \ + unsigned long __port = (a) + (r); \ + u16 *__p = (u16 *)(p); \ + int __l = (l); \ + insw(__port, __p, __l); \ + while (__l > 0) { \ + *__p = swab16(*__p); \ + __p++; \ + __l--; \ + } \ + } while (0) +#define SMC_outsw(a, r, p, l) \ + do { \ + unsigned long __port = (a) + (r); \ + u16 *__p = (u16 *)(p); \ + int __l = (l); \ + while (__l > 0) { \ + /* Believe it or not, the swab isn't needed. */ \ + outw( /* swab16 */ (*__p++), __port); \ + __l--; \ + } \ + } while (0) +#define set_irq_type(irq, type) + +#elif defined(CONFIG_SA1100_ASSABET) + +#include + +/* We can only do 8-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 0 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +/* The first two address lines aren't connected... */ +#define SMC_IO_SHIFT 2 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) +#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) + +#elif defined(CONFIG_ARCH_INNOKOM) || \ + defined(CONFIG_MACH_MAINSTONE) || \ + defined(CONFIG_ARCH_PXA_IDP) || \ + defined(CONFIG_ARCH_RAMSES) + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 1 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 +#define SMC_USE_PXA_DMA 1 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) +#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) + +/* We actually can't write halfwords properly if not word aligned */ +static inline void +SMC_outw(u16 val, unsigned long ioaddr, int reg) +{ + if (reg & 2) { + unsigned int v = val << 16; + v |= readl(ioaddr + (reg & ~2)) & 0xffff; + writel(v, ioaddr + (reg & ~2)); + } else { + writew(val, ioaddr + reg); + } +} + +#elif defined(CONFIG_ISA) + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 + +#define SMC_inb(a, r) inb((a) + (r)) +#define SMC_inw(a, r) inw((a) + (r)) +#define SMC_outb(v, a, r) outb(v, (a) + (r)) +#define SMC_outw(v, a, r) outw(v, (a) + (r)) +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#else + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 1 +#define SMC_NOWAIT 1 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) +#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) + +#define RPC_LSA_DEFAULT RPC_LED_100_10 +#define RPC_LSB_DEFAULT RPC_LED_TX_RX + +#endif + + +#ifdef SMC_USE_PXA_DMA +/* + * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is + * always happening in irq context so no need to worry about races. TX is + * different and probably not worth it for that reason, and not as critical + * as RX which can overrun memory and lose packets. + */ +#include +#include + +#ifdef SMC_insl +#undef SMC_insl +#define SMC_insl(a, r, p, l) \ + smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) +static inline void +smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma, + u_char *buf, int len) +{ + dma_addr_t dmabuf; + + /* fallback if no DMA available */ + if (dma == (unsigned char)-1) { + readsl(ioaddr + reg, buf, len); + return; + } + + /* 64 bit alignment is required for memory to memory DMA */ + if ((long)buf & 4) { + *((u32 *)buf)++ = SMC_inl(ioaddr, reg); + len--; + } + + len *= 4; + dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE); + DCSR(dma) = DCSR_NODESC; + DTADR(dma) = dmabuf; + DSADR(dma) = physaddr + reg; + DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | + DCMD_WIDTH4 | (DCMD_LENGTH & len)); + DCSR(dma) = DCSR_NODESC | DCSR_RUN; + while (!(DCSR(dma) & DCSR_STOPSTATE)); + DCSR(dma) = 0; + dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE); +} +#endif + +#ifdef SMC_insw +#undef SMC_insw +#define SMC_insw(a, r, p, l) \ + smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) +static inline void +smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma, + u_char *buf, int len) +{ + dma_addr_t dmabuf; + + /* fallback if no DMA available */ + if (dma == (unsigned char)-1) { + readsw(ioaddr + reg, buf, len); + return; + } + + /* 64 bit alignment is required for memory to memory DMA */ + while ((long)buf & 6) { + *((u16 *)buf)++ = SMC_inw(ioaddr, reg); + len--; + } + + len *= 2; + dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE); + DCSR(dma) = DCSR_NODESC; + DTADR(dma) = dmabuf; + DSADR(dma) = physaddr + reg; + DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | + DCMD_WIDTH2 | (DCMD_LENGTH & len)); + DCSR(dma) = DCSR_NODESC | DCSR_RUN; + while (!(DCSR(dma) & DCSR_STOPSTATE)); + DCSR(dma) = 0; + dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE); +} +#endif + +static void +smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs) +{ + DCSR(dma) = 0; +} +#endif /* SMC_USE_PXA_DMA */ + + +/* Because of bank switching, the LAN91x uses only 16 I/O ports */ +#ifndef SMC_IO_SHIFT +#define SMC_IO_SHIFT 0 +#endif +#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) +#endif + +/* + * Bank Select Register (identical in all banks) + * + * yyyy yyyy 0000 00xx + * xx = bank number + * yyyy yyyy = 0x33, for identification purposes. + */ +#define SMC_REG_BANK_SELECT 14 + +/* + * Transmit Control Register (Bank 0) + */ +#define SMC_REG_TCR 0x0000 + +#define TCR_ENABLE 0x0001 /* When 1 we can transmit */ +#define TCR_LOOP 0x0002 /* Controls output pin LBK */ +#define TCR_FORCOL 0x0004 /* When 1 will force a collision */ +#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ +#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ +#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ +#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ +#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ +#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ +#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ +#define TCR_CLEAR 0x0000 /* do NOTHING */ + +#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) + +/* + * EPH Status Register (Bank 0) + */ +#define SMC_REG_ES 0x0002 + +#define ES_TX_SUC 0x0001 /* Last TX was successful */ +#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ +#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ +#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ +#define ES_16COL 0x0010 /* 16 Collisions Reached */ +#define ES_SQET 0x0020 /* Signal Quality Error Test */ +#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ +#define ES_TXDEFR 0x0080 /* Transmit Deferred */ +#define ES_LATCOL 0x0200 /* Late collision detected on last tx */ +#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ +#define ES_EXC_DEF 0x0800 /* Excessive Deferral */ +#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ +#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ +#define ES_TXUNRN 0x8000 /* Tx Underrun */ + +/* + * Receive Control Register (Bank 0) + */ +#define SMC_REG_RCR 0x0004 + +#define SMC_REG_RCR 0x0004 +#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ +#define RCR_PRMS 0x0002 /* Enable promiscuous mode */ +#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ +#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ +#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ +#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ +#define RCR_FILT_CAR 0x0400 /* When set filters lead. 12 bits of carrier*/ +#define RCR_SOFTRST 0x8000 /* resets the chip */ +#define RCR_CLEAR 0x0000 /* set it to a base state */ + +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) + +/* + * Counter Register (Bank 0) + */ +#define SMC_REG_COUNTER 0x0006 + +/* + * Memory Information Register (Bank 0) + */ +#define SMC_REG_MIR 0x0008 + +/* + * Receive/Phy Control Register (Bank 0) + */ +#define SMC_REG_RPC 0x000A + +#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ +#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ +#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ +#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ +#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ +#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps lnk detect*/ +#define RPC_LED_RES (0x01) /* LED = Reserved */ +#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ +#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ +#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ +#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ +#define RPC_LED_TX (0x06) /* LED = TX packet occurred */ +#define RPC_LED_RX (0x07) /* LED = RX packet occurred */ + +#ifndef RPC_LSA_DEFAULT +#define RPC_LSA_DEFAULT RPC_LED_100 +#endif +#ifndef RPC_LSB_DEFAULT +#define RPC_LSB_DEFAULT RPC_LED_FD +#endif + +#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) + +/* + * Configuration Register (Bank 1) + */ +#define SMC_REG_CONFIG 0x0000 +#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ +#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ +#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ +#define CONFIG_EPH_PWR_EN 0x8000 /* When 0 EPH goes into low power mode */ + +/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ +#define CONFIGREG_DEFAULT (CONFIG_EPH_PWR_EN) + +/* + * Base Address Register (Bank 1) + */ +#define SMC_REG_BASEADDR 0x0002 + +/* + * Individual Address Registers (Bank 1) + */ +#define SMC_REG_ADDR0 0x0004 +#define SMC_REG_ADDR1 0x0006 +#define SMC_REG_ADDR2 0x0008 + + +/* + * General Purpose Register (Bank 1) + */ +#define SMC_REG_GP 0x000A + + +/* + * Control Register (Bank 1) + */ +#define SMC_REG_CTL 0x000C + +#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ +#define CTL_AUTO_REL 0x0800 /* When 1 tx pages are released automatically*/ +#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ +#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ +#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ +#define CTL_EEPROM_SEL 0x0004 /* Controls EEPROM reload & store */ +#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ +#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ + +/* + * MMU Command Register (Bank 2) + */ +#define SMC_REG_MMU_CMD 0x0000 + +#define MC_BUSY 1 /* 1 = the last release has not completed */ +#define MC_NOP (0<<5) /* No Op */ +#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ +#define MC_RESET (2<<5) /* Reset MMU to initial state */ +#define MC_REMOVE (3<<5) /* Remove the current rx packet */ +#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ +#define MC_FREEPKT (5<<5) /* Release packet in PNR register */ +#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ +#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ + +/* + * Packet Number Register (Bank 2) + */ +#define SMC_REG_PN 0x0002 + +/* + * Allocation Result Register (Bank 2) + */ +#define SMC_REG_AR 0x0003 +#define AR_FAILED 0x80 /* Alocation Failed */ + + +/* + * TX FIFO Ports Register (Bank 2) + */ +#define SMC_REG_TXFIFO 0x0004 +#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ + +/* + * RX FIFO Ports Register (Bank 2) + */ +#define SMC_REG_RXFIFO 0x0005 +#define RXFIFO_REMPTY 0x80 /* RX FIFO Empty */ + +/* + * FIFO Reg (Bank 2) + */ +#define SMC_REG_FIFO 0x0004 + +/* + * Pointer Register (Bank 2) + */ +#define SMC_REG_PTR 0x0006 +#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ +#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ +#define PTR_READ 0x2000 /* When 1 the operation is a read */ + + +/* + * Data Register (Bank 2) + */ +#define SMC_REG_DATA 0x0008 + +/* + * Interrupt Status/Acknowledge Register (Bank 2) + */ +#define SMC_REG_INT 0x000C + +/* + * Interrupt Mask Register (Bank 2) + */ +#define SMC_REG_IM 0x000D +#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ +#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ +#define IM_EPH_INT 0x20 /* Set by Ethernet Protocol Handler section */ +#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ +#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ +#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ +#define IM_TX_INT 0x02 /* Transmit Interrupt */ +#define IM_RCV_INT 0x01 /* Receive Interrupt */ + +/* + * Multicast Table Registers (Bank 3) + */ +#define SMC_REG_MCAST1 0x0000 +#define SMC_REG_MCAST2 0x0002 +#define SMC_REG_MCAST3 0x0004 +#define SMC_REG_MCAST4 0x0006 + +/* + * Management Interface Register (MII) (Bank 3) + */ +#define SMC_REG_MII 0x0008 +#define MII_MSK_CRS100 0x4000 /* Disables CRS100 det. during tx half dup */ +#define MII_MDOE 0x0008 /* MII Output Enable */ +#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ +#define MII_MDI 0x0002 /* MII Input, pin MDI */ +#define MII_MDO 0x0001 /* MII Output, pin MDO */ + +/* + * Revision Register (Bank 3) + * + * high: chip id low: rev # + */ +#define SMC_REG_REV 0x000A + +/* + * Early RCV Register (Bank 3) + * + * this is NOT on SMC9192 + */ +#define SMC_REG_ERCV 0x000C +#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ +#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ + + +/* + * External Register (Bank 7) + */ +#define SMC_REG_EXT 0x0000 + +#define CHIP_9192 3 +#define CHIP_9194 4 +#define CHIP_9195 5 +#define CHIP_9196 6 +#define CHIP_91100 7 +#define CHIP_91100FD 8 +#define CHIP_91111FD 9 + +static const char * chip_ids[ 16 ] = { + NULL, NULL, NULL, + /* 3 */ "SMC91C90/91C92", + /* 4 */ "SMC91C94", + /* 5 */ "SMC91C95", + /* 6 */ "SMC91C96", + /* 7 */ "SMC91C100", + /* 8 */ "SMC91C100FD", + /* 9 */ "SMC91C11xFD", + NULL, NULL, NULL, + NULL, NULL, NULL}; + + +/* + * Transmit status bits + */ +#define TS_SUCCESS 0x0001 +#define TS_LOSTCAR 0x0400 +#define TS_LATCOL 0x0200 +#define TS_16COL 0x0010 + +/* + * Receive status bits + */ +#define RS_ALGNERR 0x8000 +#define RS_BRODCAST 0x4000 +#define RS_BADCRC 0x2000 +#define RS_ODDFRAME 0x1000 +#define RS_TOOLONG 0x0800 +#define RS_TOOSHORT 0x0400 +#define RS_MULTICAST 0x0001 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) + + +/* + * PHY IDs + * LAN83C183 == LAN91C111 Internal PHY + */ +#define PHY_LAN83C183 0x0016f840 +#define PHY_LAN83C180 0x02821c50 + +/* + * PHY Register Addresses (LAN91C111 Internal PHY) + * + * Generic PHY registers can be found in + * + * These phy registers are specific to our on-board phy. + */ + +/* PHY Configuration Register 1 */ +#define PHY_CFG1_REG 0x10 +#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled +#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled +#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down +#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler +#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable +#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled +#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) +#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db +#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time + + +// PHY Configuration Register 2 +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled +#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled +#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) +#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo + +// PHY Status Output (and Interrupt status) Register +#define PHY_INT_REG 0x12 // Status Output (Interrupt Status) +#define PHY_INT_INT 0x8000 // 1=bits have changed since last read +#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected +#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync +#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx +#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx +#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx +#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected +#define PHY_INT_JAB 0x0100 // 1=Jabber detected +#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode +#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex + +// PHY Interrupt/Status Mask Register +#define PHY_MASK_REG 0x13 // Interrupt Mask +// Uses the same bit definitions as PHY_INT_REG + + +/* + * SMC91C96 ethernet config and status registers. + * These are in the "attribute" space. + */ +#define ECOR 0x8000 +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x04 +#define ECOR_ENABLE 0x01 + +#define ECSR 0x8002 +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 + +#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) + +#if 0 +/* + * Macros to abstract register access according to the data bus + * capabilities. Please use those and not the in/out primitives. + * Note: the following macros do *not* select the bank -- this must + * be done separately as needed in the main code. The SMC_REG() macro + * only uses the bank argument for debugging purposes (when enabled). + */ + +#if SMC_DEBUG > 0 +#define SMC_REG(reg, bank) \ + ({ \ + int __b = SMC_CURRENT_BANK(); \ + if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ + printk( "%s: bank reg screwed (0x%04x)\n", \ + CARDNAME, __b ); \ + BUG(); \ + } \ + reg<> 8) +#define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF) +#define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8) +#define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF) +#define SMC_ACK_INT(x) \ + do { \ + unsigned long __flags; \ + int __mask; \ + local_irq_save(__flags); \ + __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ + SMC_outw( __mask | (x), ioaddr, INT_REG ); \ + local_irq_restore(__flags); \ + } while (0) +#define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8) +#define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG ) +#endif + +#define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT ) +#define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT ) +#define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG ) +#define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG ) +#define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG ) +#define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG ) +#define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG ) +#define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG ) +#define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG ) +#define SMC_GET_MII() SMC_inw( ioaddr, MII_REG ) +#define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG ) +#define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG ) +#define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG ) +#define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG ) +#define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG ) +#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG ) +#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG ) +#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG ) +#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG ) +#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG ) +#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG ) +#define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG ) +#define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG ) +#define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG ) +#define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG ) + +#ifndef SMC_GET_MAC_ADDR +#define SMC_GET_MAC_ADDR(addr) \ + do { \ + unsigned int __v; \ + __v = SMC_inw( ioaddr, ADDR0_REG ); \ + addr[0] = __v; addr[1] = __v >> 8; \ + __v = SMC_inw( ioaddr, ADDR1_REG ); \ + addr[2] = __v; addr[3] = __v >> 8; \ + __v = SMC_inw( ioaddr, ADDR2_REG ); \ + addr[4] = __v; addr[5] = __v >> 8; \ + } while (0) +#endif + +#define SMC_SET_MAC_ADDR(addr) \ + do { \ + SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ + SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ + SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ + } while (0) + +#define SMC_CLEAR_MCAST() \ + do { \ + SMC_outw( 0, ioaddr, MCAST_REG1 ); \ + SMC_outw( 0, ioaddr, MCAST_REG2 ); \ + SMC_outw( 0, ioaddr, MCAST_REG3 ); \ + SMC_outw( 0, ioaddr, MCAST_REG4 ); \ + } while (0) +#define SMC_SET_MCAST(x) \ + do { \ + unsigned char *mt = (x); \ + SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ + SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ + SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ + SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ + } while (0) + +#if SMC_CAN_USE_32BIT +/* + * Some setups just can't write 8 or 16 bits reliably when not aligned + * to a 32 bit boundary. I tell you that exists! + * We re-do the ones here that can be easily worked around if they can have + * their low parts written to 0 without adverse effects. + */ +#undef SMC_SELECT_BANK +#define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<> 16; \ + } while (0) +#else +#define SMC_PUT_PKT_HDR(status, length) \ + do { \ + SMC_outw( status, ioaddr, DATA_REG ); \ + SMC_outw( length, ioaddr, DATA_REG ); \ + } while (0) +#define SMC_GET_PKT_HDR(status, length) \ + do { \ + (status) = SMC_inw( ioaddr, DATA_REG ); \ + (length) = SMC_inw( ioaddr, DATA_REG ); \ + } while (0) +#endif + +#if SMC_CAN_USE_32BIT +#define SMC_PUSH_DATA(p, l) \ + do { \ + char *__ptr = (p); \ + int __len = (l); \ + if (__len >= 2 && (long)__ptr & 2) { \ + __len -= 2; \ + SMC_outw( *((u16 *)__ptr)++, ioaddr, DATA_REG );\ + } \ + SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \ + if (__len & 2) { \ + __ptr += (__len & ~3); \ + SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ + } \ + } while (0) +#define SMC_PULL_DATA(p, l) \ + do { \ + char *__ptr = (p); \ + int __len = (l); \ + if ((long)__ptr & 2) { \ + /* \ + * We want 32bit alignment here. \ + * Since some buses perform a full 32bit \ + * fetch even for 16bit data we can't use \ + * SMC_inw() here. Back both source (on chip \ + * and destination) pointers of 2 bytes. \ + */ \ + (long)__ptr &= ~2; \ + __len += 2; \ + SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \ + } \ + __len += 2; \ + SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \ + } while (0) +#elif SMC_CAN_USE_16BIT +#define SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 ) +#define SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 ) +#elif SMC_CAN_USE_8BIT +#define SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l ) +#define SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l ) +#endif + +#if ! SMC_CAN_USE_16BIT +#define SMC_outw(x, ioaddr, reg) \ + do { \ + unsigned int __val16 = (x); \ + SMC_outb( __val16, ioaddr, reg ); \ + SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ + } while (0) +#define SMC_inw(ioaddr, reg) \ + ({ \ + unsigned int __val16; \ + __val16 = SMC_inb( ioaddr, reg ); \ + __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ + __val16; \ + }) +#endif +#endif + +/* ------------------------------------------------------------------------ */ +/* new functions ... */ +/* ------------------------------------------------------------------------ */ + +/** + * this enables an interrupt in the interrupt mask register + * + * FIXME: do {} while(0) ? + */ +static inline void smc_enable_int(struct net_device *dev, u8 mask) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&lp->lock, flags); + writew(readw(lp->ioaddr+SMC_REG_IM) | (mask<<8), lp->ioaddr+SMC_REG_IM); + spin_unlock_irqrestore(&lp->lock, flags); + + return; +} + +/** + * this disables an interrupt in the interrupt mask register + * + * FIXME: do {} while(0) ? + */ +static inline void smc_disable_int(struct net_device *dev, u8 mask) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&lp->lock, flags); + writew(readw(lp->ioaddr+SMC_REG_IM) & ~((u16)mask<<8), lp->ioaddr+SMC_REG_IM); + spin_unlock_irqrestore(&lp->lock, flags); + + return; +} + +/** + * Wait while MMU is busy. This is usually in the order of a few nanosecs + * if at all, but let's avoid deadlocking the system if the hardware + * decides to go south. + * + * FIXME: why do {} while (0)? + */ +static inline void smc_wait_mmu_busy(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + /* FIXME: why does an uncased readw work here? */ + if (unlikely(readw(lp->ioaddr+SMC_REG_MMU_CMD) & MC_BUSY)) { + unsigned long timeout = jiffies+2; + + while (readw(lp->ioaddr+SMC_REG_MMU_CMD) & MC_BUSY) { + if (time_after(jiffies,timeout)) { + printk("%s: timeout waiting for MMU\n", dev->name); + break; + } + cpu_relax(); + } + } + + return; +} + +static inline void smc_select_bank(struct net_device *dev, u8 bank) +{ + struct smc_local *lp = netdev_priv(dev); + writew(bank, lp->ioaddr + (SMC_REG_BANK_SELECT<addrshift)); + return; +} + +static inline void smc_set_rcr(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_RCR<addrshift)); + return; +} + +static inline u16 smc_get_int_mask(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_INT<addrshift)) >> 8; +} + +static inline void smc_set_int_mask(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val << 8, lp->ioaddr + (SMC_REG_INT<addrshift)); + return; +} + +static inline void smc_set_tcr(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_TCR<addrshift)); + return; +} + +static inline u16 smc_get_ctl(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_CTL<addrshift)); +} + +static inline void smc_set_ctl(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_CTL<addrshift)); + return; +} + +static inline u16 smc_get_mmu_cmd(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_MMU_CMD<addrshift)); +} + +static inline void smc_set_mmu_cmd(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_MMU_CMD<addrshift)); + return; +} + +static inline u16 smc_get_config(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_CONFIG<addrshift)); +} + +static inline void smc_set_config(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_CONFIG<addrshift)); + return; +} + +static inline u16 smc_get_ptr(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_PTR<addrshift)); +} + +static inline void smc_set_ptr(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_PTR<addrshift)); + return; +} + +static inline void smc_get_pkt_hdr(struct net_device *dev, u16 *status, + u16 *length) +{ + struct smc_local *lp = netdev_priv(dev); + if (lp->iomode & SMC_IO_CAN_16BIT) + { + *status = readw(lp->ioaddr + (SMC_REG_DATA<addrshift)); + *length = readw(lp->ioaddr + (SMC_REG_DATA<addrshift)); + } + else + { + u32 val = readl(lp->ioaddr + (SMC_REG_DATA<addrshift)); + *status = val & 0xffff; + *length = val >> 16; + } + return; +} + +static inline void smc_put_pkt_hdr(struct net_device *dev, u16 status, + u16 length) +{ + struct smc_local *lp = netdev_priv(dev); + if (lp->iomode & SMC_IO_CAN_16BIT) + { + writew(status, lp->ioaddr + (SMC_REG_DATA<addrshift)); + writew(length, lp->ioaddr + (SMC_REG_DATA<addrshift)); + } + else + { + writel(status | length << 16, + lp->ioaddr + (SMC_REG_DATA<addrshift)); + } + return; +} + +static inline u16 smc_get_ar(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_AR<addrshift)); +} + +static inline u16 smc_get_pn(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_PN<addrshift)); +} + +static inline void smc_set_pn(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_PN<addrshift)); + return; +} + +static inline void smc_ack_int(struct net_device *dev, u8 val) +{ + struct smc_local *lp = netdev_priv(dev); + unsigned long flags; + u16 mask; + + local_irq_save(flags); + mask = readw(lp->ioaddr + (SMC_REG_INT<addrshift)); + writew(val | mask, lp->ioaddr + (SMC_REG_INT<addrshift)); + local_irq_restore(flags); +} + +static inline u16 smc_current_bank(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_BANK_SELECT<addrshift)); +} + +static inline u16 smc_get_int(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_INT<addrshift)) & 0xff; +} + +static inline u16 smc_get_rxfifo(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_FIFO<addrshift)) >> 8; +} + +static inline u16 smc_get_txfifo(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_FIFO<addrshift)) & 0xff; +} + +static inline u16 smc_get_fifo(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_FIFO<addrshift)); +} + +static inline u16 smc_get_mii(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_MII<addrshift)); +} + +static inline void smc_set_mii(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_MII<addrshift)); + return; +} + +static inline u16 smc_get_mir(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_MIR<addrshift)); +} + +static inline void smc_set_mir(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_MIR<addrshift)); + return; +} + +static inline void smc_set_rpc(struct net_device *dev, u16 val) +{ + struct smc_local *lp = netdev_priv(dev); + writew(val, lp->ioaddr + (SMC_REG_RPC<addrshift)); + return; +} + +static inline u16 smc_es_link_ok(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_ES<addrshift)) & + ES_LINK_OK ? 1 : 0; +} + +static inline u16 smc_get_counter(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_COUNTER<addrshift)); +} + +static inline void smc_set_mcast(struct net_device *dev, u8 *mt) +{ + struct smc_local *lp = netdev_priv(dev); + + writew(mt[0] | (mt[1] << 8), lp->ioaddr + (SMC_REG_MCAST1<addrshift)); + writew(mt[2] | (mt[3] << 8), lp->ioaddr + (SMC_REG_MCAST2<addrshift)); + writew(mt[4] | (mt[5] << 8), lp->ioaddr + (SMC_REG_MCAST3<addrshift)); + writew(mt[6] | (mt[7] << 8), lp->ioaddr + (SMC_REG_MCAST4<addrshift)); + return; +} + +static inline void smc_clear_mcast(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + + writew(0, lp->ioaddr + (SMC_REG_MCAST1<addrshift)); + writew(0, lp->ioaddr + (SMC_REG_MCAST2<addrshift)); + writew(0, lp->ioaddr + (SMC_REG_MCAST3<addrshift)); + writew(0, lp->ioaddr + (SMC_REG_MCAST4<addrshift)); + return; +} + +static inline void smc_get_mac_addr(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + u8 *mac = dev->dev_addr; + u16 tmp; + + tmp = readw(lp->ioaddr + (SMC_REG_ADDR0<addrshift)); + mac[0] = tmp; + mac[1] = tmp >> 8; + tmp = readw(lp->ioaddr + (SMC_REG_ADDR1<addrshift)); + mac[2] = tmp; + mac[3] = tmp >> 8; + tmp = readw(lp->ioaddr + (SMC_REG_ADDR2<addrshift)); + mac[4] = tmp; + mac[5] = tmp >> 8; + return; +} + +static inline void smc_set_mac_addr(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + u8 *mac = dev->dev_addr; + + writew(mac[0] | (mac[1] << 8), lp->ioaddr + (SMC_REG_ADDR0<addrshift)); + writew(mac[2] | (mac[3] << 8), lp->ioaddr + (SMC_REG_ADDR1<addrshift)); + writew(mac[4] | (mac[5] << 8), lp->ioaddr + (SMC_REG_ADDR2<addrshift)); + return; +} + +static inline u16 smc_get_base(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_BASEADDR<addrshift)); +} + +static inline u16 smc_get_rev(struct net_device *dev) +{ + struct smc_local *lp = netdev_priv(dev); + return readw(lp->ioaddr + (SMC_REG_REV<addrshift)); +} + +static inline void smc_pull_data(struct net_device *dev, + unsigned char *data, u16 len) +{ + struct smc_local *lp = netdev_priv(dev); + + if (lp->iomode & SMC_IO_CAN_16BIT) + { + u16 i; + + for (i = 0; i < len/2; i++) + { + ((u16 *) data)[i] = readw(lp->ioaddr + (SMC_REG_DATA<addrshift)); + } +// FIXME: use readsw () +// readsw(lp->ioaddr + (SMC_REG_DATA<addrshift), data, len); + } + else + { + if ((u32) data & 2) + { + (u32) data &= ~2; + len += 2; + smc_set_ptr (dev, 2|PTR_READ|PTR_RCV|PTR_AUTOINC); + } + + readsl(lp->ioaddr + (SMC_REG_DATA<addrshift), data, len); + } + + return; +} + +static inline void smc_push_data(struct net_device *dev, + unsigned char *data, u16 len) +{ + struct smc_local *lp = netdev_priv(dev); + + if (lp->iomode & SMC_IO_CAN_16BIT) + { + writesw(lp->ioaddr + (SMC_REG_DATA<addrshift), data, len >> 1); + } + else + { + if (len >= 2 && (u32) data & 2) + { + len -= 2; + writew(*((u16 *) data)++, lp->ioaddr + (SMC_REG_DATA<addrshift)); + } + writesl(lp->ioaddr + (SMC_REG_DATA<addrshift), data, len); + } + + return; +} + +#endif /* _SMC91X_H_ */ diff -x .svn -urN linux-2.6.8-rc2/drivers/net/smc91x-old.c linux-2.6.8-rc2-pnp1/drivers/net/smc91x-old.c --- linux-2.6.8-rc2/drivers/net/smc91x-old.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/smc91x-old.c 2004-07-27 14:01:27.000000000 +0200 @@ -0,0 +1,2188 @@ +/*------------------------------------------------------------------------ + . smc91x.c + . This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. + . + . Copyright (C) 1996 by Erik Stahlman + . Copyright (C) 2001 Standard Microsystems Corporation + . Developed by Simple Network Magic Corporation + . Copyright (C) 2003 Monta Vista Software, Inc. + . Unified SMC91x driver by Nicolas Pitre + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + . Arguments: + . io = for the base address + . irq = for the IRQ + . nowait = 0 for normal wait states, 1 eliminates additional wait states + . + . original author: + . Erik Stahlman + . + . hardware multicast code: + . Peter Cammaert + . + . contributors: + . Daris A Nevil + . Nicolas Pitre + . + . History: + . 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet + . 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" + . 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 + . 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 + . 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 + . 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support + . 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, + . more bus abstraction, big cleanup, etc. + . 29/09/03 Russell King - add driver model support + . - ethtool support + . - convert to use generic MII interface + . - add link up/down notification + . - don't try to handle full negotiation in + . smc_phy_configure + . - clean up (and fix stack overrun) in PHY + . MII read/write functions + ----------------------------------------------------------------------------*/ + +static const char version[] = + "smc91x.c: v1.0, mar 07 2003 by Nicolas Pitre \n"; + +/* Debugging level */ +#ifndef SMC_DEBUG +#define SMC_DEBUG 0 +#endif + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#ifdef CONFIG_PM +#include +#endif + +#include +#include +#include + +#ifdef CONFIG_SA1100_ASSABET +#include +#include +#endif + +#include "smc91x-old.h" + +#if 0 +#define GPIO_SET *(volatile unsigned long *)0xfc900000 +#define GPIO_CLR *(volatile unsigned long *)0xfc900004 +#define GPIO_DIR *(volatile unsigned long *)0xfc900008 + +#define DEBUG_DIR(x) do { GPIO_DIR = (x); } while (0) +#define DEBUG_CLR(x) do { GPIO_CLR = (x); } while (0) +#define DEBUG_SET(x) do { GPIO_SET = (x); } while (0) +#else +#define DEBUG_DIR(x) do { } while (0) +#define DEBUG_CLR(x) do { } while (0) +#define DEBUG_SET(x) do { } while (0) +#endif + +#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS +#define LUBBOCK_ETH_VIRT (0xf1000000) + +#ifdef CONFIG_ISA +/* + . the LAN91C111 can be at any of the following port addresses. To change, + . for a slightly different card, you can add it to the array. Keep in + . mind that the array must end in zero. +*/ +static unsigned int smc_portlist[] __initdata = { + 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0, + 0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0, 0 +}; +#endif /* CONFIG_ISA */ + +#ifndef SMC_IOADDR +# define SMC_IOADDR -1 +#endif +static int io = SMC_IOADDR; + +#ifndef SMC_IRQ +# define SMC_IRQ -1 +#endif +static int irq = SMC_IRQ; + +#ifndef SMC_NOWAIT +# define SMC_NOWAIT 0 +#endif +static int nowait = SMC_NOWAIT; + +MODULE_PARM(io, "i"); +MODULE_PARM(irq, "i"); +MODULE_PARM(nowait, "i"); +MODULE_PARM_DESC(io, "I/O base address"); +MODULE_PARM_DESC(irq, "IRQ number"); +MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); + + +/*------------------------------------------------------------------------ + . + . The internal workings of the driver. If you are changing anything + . here with the SMC stuff, you should have the datasheet and know + . what you are doing. + . + -------------------------------------------------------------------------*/ +#define CARDNAME "smc91x" + +// Use power-down feature of the chip +#define POWER_DOWN 1 + +/* + . Wait time for memory to be free. This probably shouldn't be + . tuned that much, as waiting for this means nothing else happens + . in the system +*/ +#define MEMORY_WAIT_TIME 16 + +/* + . This selects whether TX packets are sent one by one to the SMC91x internal + . memory and throttled until transmission completes. This may prevent + . RX overruns a litle by keeping much of the memory free for RX packets + . but to the expense of reduced TX throughput and increased IRQ overhead. + . Note this is not a cure for a too slow data bus or too high IRQ latency. + */ +#ifdef CONFIG_ARM_SMC91X_THROTTLE_TX +#define THROTTLE_TX_PKTS 1 +#else +#define THROTTLE_TX_PKTS 0 +#endif + +/* + * The MII clock high/low times. 2x this number gives the MII clock period + * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) + */ +#define MII_DELAY 1 + +/* store this information for the driver.. */ +struct smc_local { + // If I have to wait until memory is available to send + // a packet, I will store the skbuff here, until I get the + // desired memory. Then, I'll send it out and free it. + struct sk_buff *saved_skb; + + // these are things that the kernel wants me to keep, so users + // can find out semi-useless statistics of how well the card is + // performing + struct net_device_stats stats; + + // version/revision of the SMC91x chip + int version; + + // Contains the current active transmission mode + int tcr_cur_mode; + + // Contains the current active receive mode + int rcr_cur_mode; + + // Contains the current active receive/phy mode + int rpc_cur_mode; + int ctl_rfduplx; + int ctl_rspeed; + + u32 msg_enable; + u32 phy_type; + struct mii_if_info mii; + spinlock_t lock; +}; + +#if SMC_DEBUG > 2 +#define PRINTK3(args...) printk(args) +#else +#define PRINTK3(args...) do { } while(0) +#endif + +#if SMC_DEBUG > 1 +#define PRINTK2(args...) printk(args) +#else +#define PRINTK2(args...) do { } while(0) +#endif + +#if SMC_DEBUG > 0 +#define PRINTK1(args...) printk(args) +#define PRINTK(args...) printk(args) +#else +#define PRINTK1(args...) do { } while(0) +#define PRINTK(args...) printk(KERN_DEBUG args) +#endif + +#if SMC_DEBUG > 3 +static void PRINT_PKT(u_char *buf, int length) +{ + int i; + int remainder; + int lines; + + lines = length / 16; + remainder = length % 16; + + for (i = 0; i < lines ; i ++) { + int cur; + for (cur = 0; cur < 8; cur++) { + u_char a, b; + a = *buf++; + b = *buf++; + printk("%02x%02x ", a, b); + } + printk("\n"); + } + for (i = 0; i < remainder/2 ; i++) { + u_char a, b; + a = *buf++; + b = *buf++; + printk("%02x%02x ", a, b ); + } + printk("\n"); +} +#else +#define PRINT_PKT(x...) do { } while(0) +#endif + + +/* this enables an interrupt in the interrupt mask register */ +#define SMC_ENABLE_INT(x) do { \ + unsigned long flags; \ + unsigned char mask; \ + spin_lock_irqsave(&lp->lock, flags); \ + mask = SMC_GET_INT_MASK(); \ + mask |= (x); \ + SMC_SET_INT_MASK(mask); \ + spin_unlock_irqrestore(&lp->lock, flags); \ +} while (0) + +/* this disables an interrupt from the interrupt mask register */ +#define SMC_DISABLE_INT(x) do { \ + unsigned long flags; \ + unsigned char mask; \ + spin_lock_irqsave(&lp->lock, flags); \ + mask = SMC_GET_INT_MASK(); \ + mask &= ~(x); \ + SMC_SET_INT_MASK(mask); \ + spin_unlock_irqrestore(&lp->lock, flags); \ +} while (0) + +/* wait while MMU is busy */ +#define SMC_WAIT_MMU_BUSY() do { \ + if (unlikely(SMC_GET_MMU_CMD() & MC_BUSY)) { \ + unsigned long timeout = jiffies + 2; \ + while (SMC_GET_MMU_CMD() & MC_BUSY) { \ + if (time_after(jiffies, timeout)) { \ + printk("%s: timeout %s line %d\n", \ + dev->name, __FILE__, __LINE__); \ + break; \ + } \ + } \ + } \ +} while (0) + + +/* this does a soft reset on the device */ +static void +smc_reset(struct net_device *dev) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int ctl; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + /* This resets the registers mostly to defaults, but doesn't + affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK( 0 ); + SMC_SET_RCR( RCR_SOFTRST ); + + /* Setup the Configuration Register */ + /* This is necessary because the CONFIG_REG is not affected */ + /* by a soft reset */ + SMC_SELECT_BANK( 1 ); + SMC_SET_CONFIG( CONFIG_DEFAULT ); + + /* Setup for fast accesses if requested */ + /* If the card/system can't handle it then there will */ + /* be no recovery except for a hard reset or power cycle */ + if (nowait) + SMC_SET_CONFIG( SMC_GET_CONFIG() | CONFIG_NO_WAIT ); + +#ifdef POWER_DOWN + /* Release from possible power-down state */ + /* Configuration register is not affected by Soft Reset */ + SMC_SELECT_BANK( 1 ); + SMC_SET_CONFIG( SMC_GET_CONFIG() | CONFIG_EPH_POWER_EN ); +#endif + + /* this should pause enough for the chip to be happy */ + udelay(1); + + /* Disable transmit and receive functionality */ + SMC_SELECT_BANK( 0 ); + SMC_SET_RCR( RCR_CLEAR ); + SMC_SET_TCR( TCR_CLEAR ); + + SMC_SELECT_BANK( 1 ); + ctl = SMC_GET_CTL() | CTL_LE_ENABLE; + + /* set the control register to automatically + release successfully transmitted packets, to make the best + use out of our limited memory */ +#if ! THROTTLE_TX_PKTS + ctl |= CTL_AUTO_RELEASE; +#else + ctl &= ~CTL_AUTO_RELEASE; +#endif + SMC_SET_CTL(ctl); + + /* Disable all interrupts */ + SMC_SELECT_BANK( 2 ); + SMC_SET_INT_MASK( 0 ); + + /* Reset the MMU */ + SMC_SET_MMU_CMD( MC_RESET ); + SMC_WAIT_MMU_BUSY(); +} + +/* Enable Interrupts, Receive, and Transmit */ +static void +smc_enable(struct net_device *dev) +{ + unsigned long ioaddr = dev->base_addr; + struct smc_local *lp = (struct smc_local *)dev->priv; + int mask; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + /* see the header file for options in TCR/RCR DEFAULT*/ + SMC_SELECT_BANK( 0 ); + SMC_SET_TCR( lp->tcr_cur_mode ); + SMC_SET_RCR( lp->rcr_cur_mode ); + + /* now, enable interrupts */ + mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; + if (lp->version >= (CHIP_91100 << 4)) + mask |= IM_MDINT; + SMC_SELECT_BANK( 2 ); + SMC_SET_INT_MASK( mask ); +} + +/* this puts the device in an inactive state */ +static void +smc_shutdown(unsigned long ioaddr) +{ + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__); + + /* no more interrupts for me */ + SMC_SELECT_BANK( 2 ); + SMC_SET_INT_MASK( 0 ); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK( 0 ); + SMC_SET_RCR( RCR_CLEAR ); + SMC_SET_TCR( TCR_CLEAR ); + +#ifdef POWER_DOWN + /* finally, shut the chip down */ + SMC_SELECT_BANK( 1 ); + SMC_SET_CONFIG( SMC_GET_CONFIG() & ~CONFIG_EPH_POWER_EN ); +#endif +} + +/* This is the procedure to handle the receipt of a packet. */ +static inline void +smc_rcv(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + unsigned int packet_number, status, packet_len; + + PRINTK3("%s: %s\n", dev->name, __FUNCTION__); + + DEBUG_SET(1); + + packet_number = SMC_GET_RXFIFO(); + if (unlikely(packet_number & RXFIFO_REMPTY)) { + PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name); + return; + } + + /* read from start of packet */ + SMC_SET_PTR( PTR_READ | PTR_RCV | PTR_AUTOINC ); + + /* First two words are status and packet length */ + SMC_GET_PKT_HDR(status, packet_len); + packet_len &= 0x07ff; /* mask off top bits */ + PRINTK2("%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", + dev->name, packet_number, status, + packet_len, packet_len); + + if (unlikely(status & RS_ERRORS)) { + lp->stats.rx_errors++; + if (status & RS_ALGNERR) + lp->stats.rx_frame_errors++; + if (status & (RS_TOOSHORT | RS_TOOLONG)) + lp->stats.rx_length_errors++; + if (status & RS_BADCRC) + lp->stats.rx_crc_errors++; + } else { + struct sk_buff *skb; + unsigned char *data; + unsigned int data_len; + + /* set multicast stats */ + if (status & RS_MULTICAST) + lp->stats.multicast++; + + /* + * Actual payload is packet_len - 4 (or 3 if odd byte). + * We want skb_reserve(2) and the final ctrl word + * (2 bytes, possibly containing the payload odd byte). + * Ence packet_len - 4 + 2 + 2. + */ + DEBUG_SET(2); + skb = dev_alloc_skb(packet_len); + if (unlikely(skb == NULL)) { + printk(KERN_NOTICE "%s: Low memory, packet dropped.\n", + dev->name); + lp->stats.rx_dropped++; + goto done; + } + DEBUG_CLR(2); + + /* Align IP header to 32 bits */ + skb_reserve(skb, 2); + + /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ + if (lp->version == 0x90) + status |= RS_ODDFRAME; + + /* + * If odd length: packet_len - 3, + * otherwise packet_len - 4. + */ + data_len = packet_len - ((status & RS_ODDFRAME) ? 3 : 4); + data = skb_put(skb, data_len); + DEBUG_SET(4); + SMC_PULL_DATA(data, packet_len - 2); + DEBUG_CLR(4); + + PRINT_PKT(data, packet_len - 2); + + dev->last_rx = jiffies; + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + DEBUG_SET(8); + netif_rx(skb); + DEBUG_CLR(8); + lp->stats.rx_packets++; + lp->stats.rx_bytes += data_len; + } + +done: + SMC_WAIT_MMU_BUSY(); + SMC_SET_MMU_CMD( MC_RELEASE ); + + DEBUG_CLR(1); +} + +/* + * This is called to actually send a packet to the chip. + * Returns non-zero when successful. + */ +static void +smc_hardware_send_packet(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + struct sk_buff *skb = lp->saved_skb; + unsigned int packet_no, len; + unsigned char *buf; + + PRINTK3("%s: %s\n", dev->name, __FUNCTION__); + + if (unlikely(!skb)) { + printk ("%s: In XMIT with no packet to send\n", dev->name); + return; + } + + packet_no = SMC_GET_AR(); + if (unlikely(packet_no & AR_FAILED)) { + printk("%s: Memory allocation failed.\n", dev->name); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_fifo_errors++; + dev_kfree_skb_any(skb); + return; + } + + /* point to the beginning of the packet */ + SMC_SET_PN( packet_no ); + SMC_SET_PTR( PTR_AUTOINC ); + + buf = skb->data; + len = skb->len; + PRINTK2("%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", + dev->name, packet_no, len, len, buf); + PRINT_PKT(buf, len); + + /* + * Send the packet length ( +6 for status words, length, and ctl. + * The card will pad to 64 bytes with zeroes if packet is too small. + */ + SMC_PUT_PKT_HDR(0, len + 6); + + /* send the actual data */ + SMC_PUSH_DATA(buf, len & ~1); + + /* Send final ctl word with the last byte if there is one */ + SMC_outw( ((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG ); + + /* and let the chipset deal with it */ + SMC_SET_MMU_CMD( MC_ENQUEUE ); + SMC_ACK_INT( IM_TX_EMPTY_INT ); + + dev->trans_start = jiffies; + dev_kfree_skb_any(skb); + lp->saved_skb = NULL; + lp->stats.tx_packets++; + lp->stats.tx_bytes += len; +} + +/* + . Since I am not sure if I will have enough room in the chip's ram + . to store the packet, I call this routine which either sends it + . now, or set the card to generates an interrupt when ready + . for the packet. + */ +static int +smc_hard_start_xmit( struct sk_buff * skb, struct net_device * dev ) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + unsigned int numPages, poll_count, status, saved_bank; + + PRINTK3("%s: %s\n", dev->name, __FUNCTION__); + + if (unlikely(lp->saved_skb != NULL)) { + /* THIS SHOULD NEVER HAPPEN. */ + printk( KERN_CRIT + "%s: Bad Craziness - sent packet while busy.\n", + dev->name ); + lp->stats.tx_errors++; + lp->stats.tx_aborted_errors++; + return 1; + } + lp->saved_skb = skb; + + /* + ** The MMU wants the number of pages to be the number of 256 bytes + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) + ** + ** The 91C111 ignores the size bits, but the code is left intact + ** for backwards and future compatibility. + ** + ** Pkt size for allocating is data length +6 (for additional status + ** words, length and ctl!) + ** + ** If odd size then last byte is included in ctl word. + */ + numPages = ((skb->len & ~1) + (6 - 1)) >> 8; + if (unlikely(numPages > 7)) { + printk("%s: Far too big packet error.\n", dev->name); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_dropped++; + dev_kfree_skb(skb); + return 0; + } + + /* now, try to allocate the memory */ + saved_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK( 2 ); + SMC_SET_MMU_CMD( MC_ALLOC | numPages ); + + /* + * Poll the chip for a short amount of time in case the + * allocation succeeds quickly. + */ + poll_count = MEMORY_WAIT_TIME; + do { + status = SMC_GET_INT(); + if (status & IM_ALLOC_INT) { + SMC_ACK_INT( IM_ALLOC_INT ); + break; + } + } while (--poll_count); + + if (!poll_count) { + /* oh well, wait until the chip finds memory later */ + netif_stop_queue(dev); + PRINTK2("%s: TX memory allocation deferred.\n", dev->name); + SMC_ENABLE_INT( IM_ALLOC_INT ); + } else { + /* Send current packet immediately.. */ +#if THROTTLE_TX_PKTS + netif_stop_queue(dev); +#endif + smc_hardware_send_packet(dev); + SMC_ENABLE_INT( IM_TX_INT | IM_TX_EMPTY_INT ); + } + + SMC_SELECT_BANK( saved_bank ); + return 0; +} + +/* + . This handles a TX interrupt, which is only called when an error + . relating to a packet is sent or CTL_AUTO_RELEASE is not set. +*/ +static void +smc_tx(struct net_device *dev) +{ + unsigned long ioaddr = dev->base_addr; + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned int saved_packet, packet_no, tx_status, pkt_len; + + PRINTK3("%s: %s\n", dev->name, __FUNCTION__); + + /* If the TX FIFO is empty then nothing to do */ + packet_no = SMC_GET_TXFIFO(); + if (unlikely(packet_no & TXFIFO_TEMPTY)) { + PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name); + return; + } + + /* select packet to read from */ + saved_packet = SMC_GET_PN(); + SMC_SET_PN( packet_no ); + + /* read the first word (status word) from this packet */ + SMC_SET_PTR( PTR_AUTOINC | PTR_READ ); + SMC_GET_PKT_HDR(tx_status, pkt_len); + PRINTK2("%s: TX STATUS 0x%04x PNR 0x%02x\n", + dev->name, tx_status, packet_no); + + if (!(tx_status & TS_SUCCESS)) + lp->stats.tx_errors++; + if (tx_status & TS_LOSTCAR) + lp->stats.tx_carrier_errors++; + if (tx_status & TS_LATCOL) { + printk( KERN_DEBUG + "%s: Late collision occurred on last xmit.\n", + dev->name); + lp->stats.tx_window_errors++; + } + + /* kill the packet */ + SMC_WAIT_MMU_BUSY(); + SMC_SET_MMU_CMD( MC_FREEPKT ); + + /* Don't restore Packet Number Reg until busy bit is cleared */ + SMC_WAIT_MMU_BUSY(); + SMC_SET_PN( saved_packet ); + + /* re-enable transmit */ + SMC_SELECT_BANK( 0 ); + SMC_SET_TCR( lp->tcr_cur_mode ); + SMC_SELECT_BANK( 2 ); +} + + +//---PHY CONTROL AND CONFIGURATION----------------------------------------- + +static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int mii_reg, mask; + + mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO); + mii_reg |= MII_MDOE; + + for (mask = 1 << (bits - 1); mask; mask >>= 1) { + if (val & mask) + mii_reg |= MII_MDO; + else + mii_reg &= ~MII_MDO; + + SMC_SET_MII(mii_reg); + udelay(MII_DELAY); + SMC_SET_MII(mii_reg | MII_MCLK); + udelay(MII_DELAY); + } +} + +static unsigned int smc_mii_in(struct net_device *dev, int bits) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int mii_reg, mask, val; + + mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO); + SMC_SET_MII(mii_reg); + + for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { + if (SMC_GET_MII() & MII_MDI) + val |= mask; + + SMC_SET_MII(mii_reg); + udelay(MII_DELAY); + SMC_SET_MII(mii_reg | MII_MCLK); + udelay(MII_DELAY); + } + + return val; +} + +/*------------------------------------------------------------ + . Reads a register from the MII Management serial interface + .-------------------------------------------------------------*/ +static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int phydata, old_bank; + + // Save the current bank, and select bank 3 + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(3); + + // Idle - 32 ones + smc_mii_out(dev, 0xffffffff, 32); + + // Start code (01) + read (10) + phyaddr + phyreg + smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); + + // Turnaround (2bits) + phydata + phydata = smc_mii_in(dev, 18); + + // Return to idle state + SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO)); + + // And select original bank + SMC_SELECT_BANK(old_bank); + + PRINTK3("%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", + __FUNCTION__, phyaddr, phyreg, phydata); + + return phydata; +} + +/*------------------------------------------------------------ + . Writes a register to the MII Management serial interface + .-------------------------------------------------------------*/ +static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, + int phydata) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int old_bank; + + // Save the current bank, and select bank 3 + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(3); + + // Idle - 32 ones + smc_mii_out(dev, 0xffffffff, 32); + + // Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata + smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); + + // Return to idle state + SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO)); + + // And select original bank + SMC_SELECT_BANK(old_bank); + + PRINTK3("%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", + __FUNCTION__, phyaddr, phyreg, phydata); +} + +/*------------------------------------------------------------ + . Finds and reports the PHY address + .-------------------------------------------------------------*/ +static void smc_detect_phy(struct net_device* dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + int phyaddr; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + lp->phy_type = 0; + + // Scan all 32 PHY addresses if necessary + for (phyaddr = 0; phyaddr < 32; ++phyaddr) { + unsigned int id1, id2; + + // Read the PHY identifiers + id1 = smc_phy_read(dev, phyaddr, MII_PHYSID1); + id2 = smc_phy_read(dev, phyaddr, MII_PHYSID2); + + PRINTK3("%s: phy_id1=0x%x, phy_id2=0x%x\n", + dev->name, id1, id2); + + // Make sure it is a valid identifier + if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && + id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { + // Save the PHY's address + lp->mii.phy_id = phyaddr; + lp->phy_type = id1 << 16 | id2; + break; + } + } + + if (lp->phy_type == 0) { + PRINTK("%s: No PHY found\n", dev->name); + return; + } + + // Set the PHY type + if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { + PRINTK("%s: PHY=LAN83C183 (LAN91C111 Internal)\n", dev->name); + } + + if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { + PRINTK("%s: PHY=LAN83C180\n", dev->name); + } +} + +/*------------------------------------------------------------ + . Waits the specified number of milliseconds - kernel friendly + .-------------------------------------------------------------*/ +static void +smc_wait_ms(unsigned int ms) +{ + if (!in_interrupt()) { + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(1 + ms * HZ / 1000); + } else { + /* if this happens it must be fixed */ + printk( KERN_WARNING "%s: busy wait while in interrupt!\n", + __FUNCTION__); + mdelay(ms); + } +} + +/*------------------------------------------------------------ + . Sets the PHY to a configuration as determined by the user + .-------------------------------------------------------------*/ +static int +smc_phy_fixed(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + int phyaddr = lp->mii.phy_id; + int bmcr, cfg1; + + PRINTK3("%s: %s\n", dev->name, __FUNCTION__); + + // Enter Link Disable state + cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); + cfg1 |= PHY_CFG1_LNKDIS; + smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); + + // Set our fixed capabilities + // Disable auto-negotiation + bmcr = 0; + + if (lp->ctl_rfduplx) + bmcr |= BMCR_FULLDPLX; + + if (lp->ctl_rspeed == 100) + bmcr |= BMCR_SPEED100; + + // Write our capabilities to the phy control register + smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); + + // Re-Configure the Receive/Phy Control register + SMC_SET_RPC( lp->rpc_cur_mode ); + + // Success + return(1); +} + +/* + * smc_phy_reset - reset the phy + * @dev: net device + * @phy: phy address + * + * Issue a software reset for the specified PHY and + * wait up to 100ms for the reset to complete. We should + * not access the PHY for 50ms after issuing the reset. + * + * The time to wait appears to be dependent on the PHY. + * + * Must be called with lp->lock locked. + */ +static int smc_phy_reset(struct net_device *dev, int phy) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned int bmcr; + int timeout; + + smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); + + for (timeout = 2; timeout; timeout--) { + spin_unlock_irq(&lp->lock); + smc_wait_ms(50); + spin_lock_irq(&lp->lock); + + bmcr = smc_phy_read(dev, phy, MII_BMCR); + if (!(bmcr & BMCR_RESET)) + break; + } + + return bmcr & BMCR_RESET; +} + +/* + * smc_phy_powerdown - powerdown phy + * @dev: net device + * @phy: phy address + * + * Power down the specified PHY + */ +static void smc_phy_powerdown(struct net_device *dev, int phy) +{ + unsigned int bmcr; + + bmcr = smc_phy_read(dev, phy, MII_BMCR); + smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); +} + +/* + * smc_phy_check_media - check the media status and adjust TCR + * @dev: net device + * @init: set true for initialisation + * + * Select duplex mode depending on negotiation state. This + * also updates our carrier state. + */ +static void smc_phy_check_media(struct net_device *dev, int init) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + + if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { + unsigned int old_bank; + + /* duplex state has changed */ + if (lp->mii.full_duplex) { + lp->tcr_cur_mode |= TCR_SWFDUP; + } else { + lp->tcr_cur_mode &= ~TCR_SWFDUP; + } + + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(0); + SMC_SET_TCR(lp->tcr_cur_mode); + SMC_SELECT_BANK(old_bank); + } +} + +/*------------------------------------------------------------ + . Configures the specified PHY through the MII management interface + . using Autonegotiation. + . Calls smc_phy_fixed() if the user has requested a certain config. + . If RPC ANEG bit is set, the media selection is dependent purely on + . the selection by the MII (either in the MII BMCR reg or the result + . of autonegotiation.) If the RPC ANEG bit is cleared, the selection + . is controlled by the RPC SPEED and RPC DPLX bits. + .-------------------------------------------------------------*/ +static void smc_phy_configure(struct net_device* dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + int phyaddr = lp->mii.phy_id; + int my_phy_caps; // My PHY capabilities + int my_ad_caps; // My Advertised capabilities + int status; + + PRINTK3("%s:smc_program_phy()\n", dev->name); + + spin_lock_irq(&lp->lock); + + // We should not be called if phy_type is zero. + if (lp->phy_type == 0) + goto smc_phy_configure_exit; + + if (smc_phy_reset(dev, phyaddr)) { + printk("%s: PHY reset timed out\n", dev->name); + goto smc_phy_configure_exit; + } + + // Enable PHY Interrupts (for register 18) + // Interrupts listed here are disabled + smc_phy_write(dev, phyaddr, PHY_MASK_REG, + PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | + PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | + PHY_INT_SPDDET | PHY_INT_DPLXDET); + + /* Configure the Receive/Phy Control register */ + SMC_SELECT_BANK( 0 ); + SMC_SET_RPC( lp->rpc_cur_mode ); + + // If the user requested no auto neg, then go set his request + if (lp->mii.force_media) { + smc_phy_fixed(dev); + goto smc_phy_configure_exit; + } + + // Copy our capabilities from MII_BMSR to MII_ADVERTISE + my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); + + if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { + printk(KERN_INFO "Auto negotiation NOT supported\n"); + smc_phy_fixed(dev); + goto smc_phy_configure_exit; + } + + my_ad_caps = ADVERTISE_CSMA; // I am CSMA capable + + if (my_phy_caps & BMSR_100BASE4) + my_ad_caps |= ADVERTISE_100BASE4; + if (my_phy_caps & BMSR_100FULL) + my_ad_caps |= ADVERTISE_100FULL; + if (my_phy_caps & BMSR_100HALF) + my_ad_caps |= ADVERTISE_100HALF; + if (my_phy_caps & BMSR_10FULL) + my_ad_caps |= ADVERTISE_10FULL; + if (my_phy_caps & BMSR_10HALF) + my_ad_caps |= ADVERTISE_10HALF; + + // Disable capabilities not selected by our user + if (lp->ctl_rspeed != 100) + my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); + + if (!lp->ctl_rfduplx) + my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); + + // Update our Auto-Neg Advertisement Register + smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); + lp->mii.advertising = my_ad_caps; + + // Read the register back. Without this, it appears that when + // auto-negotiation is restarted, sometimes it isn't ready and + // the link does not come up. + status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); + + PRINTK2("%s: phy caps=%x\n", dev->name, my_phy_caps); + PRINTK2("%s: phy advertised caps=%x\n", dev->name, my_ad_caps); + + // Restart auto-negotiation process in order to advertise my caps + smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); + + smc_phy_check_media(dev, 1); + +smc_phy_configure_exit: + // Exit auto-negotiation + spin_unlock_irq(&lp->lock); +} + +/************************************************************************* + . smc_phy_interrupt + . + . Purpose: Handle interrupts relating to PHY register 18. This is + . called from the "hard" interrupt handler under our private spinlock. + . + ************************************************************************/ +static void +smc_phy_interrupt(struct net_device* dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + int phyaddr = lp->mii.phy_id; + int phy18; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + if (lp->phy_type == 0) + return; + + for(;;) { + smc_phy_check_media(dev, 0); + + // Read PHY Register 18, Status Output + phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); + if ((phy18 & PHY_INT_INT) == 0) + break; + } +} + +//--- END PHY CONTROL AND CONFIGURATION------------------------------------- + +static void smc_10bt_check_media(struct net_device *dev, int init) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + unsigned int old_carrier, new_carrier, old_bank; + + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(0); + old_carrier = netif_carrier_ok(dev) ? 1 : 0; + new_carrier = SMC_inw(ioaddr, EPH_STATUS_REG) & ES_LINK_OK ? 1 : 0; + + if (init || (old_carrier != new_carrier)) { + if (!new_carrier) { + netif_carrier_off(dev); + } else { + netif_carrier_on(dev); + } + if (netif_msg_link(lp)) + printk(KERN_INFO "%s: link %s\n", dev->name, + new_carrier ? "up" : "down"); + } + SMC_SELECT_BANK(old_bank); +} + +static void smc_eph_interrupt(struct net_device *dev) +{ + unsigned long ioaddr = dev->base_addr; + unsigned int old_bank, ctl; + + smc_10bt_check_media(dev, 0); + + old_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(1); + + ctl = SMC_GET_CTL(); + SMC_SET_CTL(ctl & ~CTL_LE_ENABLE); + SMC_SET_CTL(ctl); + + SMC_SELECT_BANK(old_bank); +} + +/* + * This is the main routine of the driver, to handle the device when + * it needs some attention. + */ +static irqreturn_t +smc_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct net_device *dev = dev_id; + unsigned long ioaddr = dev->base_addr; + struct smc_local *lp = (struct smc_local *)dev->priv; + int status, mask, timeout, card_stats; + int saved_bank, saved_pointer, handled = 0; + + PRINTK3("%s: %s\n", dev->name, __FUNCTION__); + + saved_bank = SMC_CURRENT_BANK(); + SMC_SELECT_BANK(2); + saved_pointer = SMC_GET_PTR(); + mask = SMC_GET_INT_MASK(); + SMC_SET_INT_MASK( 0 ); + + /* set a timeout value, so I don't stay here forever */ + timeout = 8; + + do { + status = SMC_GET_INT(); + + PRINTK2("%s: IRQ 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", + dev->name, status, mask, + ({ int meminfo; SMC_SELECT_BANK(0); + meminfo = SMC_GET_MIR(); + SMC_SELECT_BANK(2); meminfo; }), + SMC_GET_FIFO()); + + status &= mask; + if (!status) + break; + + spin_lock(&lp->lock); + + handled = 1; + + if (status & IM_RCV_INT) { + PRINTK3("%s: RX irq\n", dev->name); + smc_rcv(dev); + } else if (status & IM_TX_INT) { + PRINTK3("%s: TX int\n", dev->name); + smc_tx(dev); + SMC_ACK_INT( IM_TX_INT ); +#if THROTTLE_TX_PKTS + netif_wake_queue(dev); +#endif + } else if (status & IM_ALLOC_INT) { + PRINTK3("%s: Allocation irq\n", dev->name); + smc_hardware_send_packet(dev); + mask |= (IM_TX_INT | IM_TX_EMPTY_INT); + mask &= ~IM_ALLOC_INT; +#if ! THROTTLE_TX_PKTS + netif_wake_queue(dev); +#endif + } else if (status & IM_TX_EMPTY_INT) { + PRINTK3("%s: TX empty\n", dev->name); + mask &= ~IM_TX_EMPTY_INT; + + /* update stats */ + SMC_SELECT_BANK( 0 ); + card_stats = SMC_GET_COUNTER(); + SMC_SELECT_BANK( 2 ); + + /* single collisions */ + lp->stats.collisions += card_stats & 0xF; + card_stats >>= 4; + + /* multiple collisions */ + lp->stats.collisions += card_stats & 0xF; + } else if (status & IM_RX_OVRN_INT) { + PRINTK1( "%s: RX overrun\n", dev->name); + SMC_ACK_INT( IM_RX_OVRN_INT ); + lp->stats.rx_errors++; + lp->stats.rx_fifo_errors++; + } else if (status & IM_EPH_INT) { + smc_eph_interrupt(dev); + } else if (status & IM_MDINT) { + SMC_ACK_INT( IM_MDINT ); + smc_phy_interrupt(dev); + } else if (status & IM_ERCV_INT ) { + SMC_ACK_INT( IM_ERCV_INT ); + PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name); + } + + spin_unlock(&lp->lock); + } while (--timeout); + + /* restore register states */ + SMC_SET_INT_MASK( mask ); + SMC_SET_PTR( saved_pointer ); + SMC_SELECT_BANK( saved_bank ); + + PRINTK3("%s: Interrupt done\n", dev->name); + + return IRQ_RETVAL(handled); +} + +/* Our watchdog timed out. Called by the networking layer */ +static void +smc_timeout(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + smc_reset(dev); + smc_enable(dev); + +#if 0 + /* Reconfiguring the PHY doesn't seem like a bad idea here, but + * it introduced a problem. Now that this is a timeout routine, + * we are getting called from within an interrupt context. + * smc_phy_configure() calls smc_wait_ms() which calls + * schedule_timeout() which calls schedule(). When schedule() + * is called from an interrupt context, it prints out + * "Scheduling in interrupt" and then calls BUG(). This is + * obviously not desirable. This was worked around by removing + * the call to smc_phy_configure() here because it didn't seem + * absolutely necessary. Ultimately, if smc_wait_ms() is + * supposed to be usable from an interrupt context (which it + * looks like it thinks it should handle), it should be fixed. + */ + /* Reconfigure the PHY */ + if (lp->phy_type != 0) + smc_phy_configure(dev); +#endif + + /* clear anything saved */ + if (lp->saved_skb != NULL) { + dev_kfree_skb (lp->saved_skb); + lp->saved_skb = NULL; + lp->stats.tx_errors++; + lp->stats.tx_aborted_errors++; + } + dev->trans_start = jiffies; + netif_wake_queue(dev); +} + +/* + . This sets the internal hardware table to filter out unwanted multicast + . packets before they take up memory. + . + . The SMC chip uses a hash table where the high 6 bits of the CRC of + . address are the offset into the table. If that bit is 1, then the + . multicast packet is accepted. Otherwise, it's dropped silently. + . + . To use the 6 bits as an offset into the table, the high 3 bits are the + . number of the 8 bit register, while the low 3 bits are the bit within + . that register. + . + . This routine is based very heavily on the one provided by Peter Cammaert. +*/ +static void +smc_setmulticast(unsigned long ioaddr, int count, struct dev_mc_list *addrs) +{ + int i; + unsigned char multicast_table[ 8 ]; + struct dev_mc_list *cur_addr; + + /* table for flipping the order of 3 bits */ + static unsigned char invert3[] = { 0, 4, 2, 6, 1, 5, 3, 7 }; + + /* start with a table of all zeros: reject all */ + memset( multicast_table, 0, sizeof( multicast_table ) ); + + cur_addr = addrs; + for ( i = 0; i < count ; i ++, cur_addr = cur_addr->next ) { + int position; + + /* do we have a pointer here? */ + if ( !cur_addr ) + break; + /* make sure this is a multicast address - shouldn't this + be a given if we have it here ? */ + if ( !( *cur_addr->dmi_addr & 1 ) ) + continue; + + /* only use the low order bits */ + position = crc32_le(~0, cur_addr->dmi_addr, 6) & 0x3f; + + /* do some messy swapping to put the bit in the right spot */ + multicast_table[invert3[position&7]] |= + (1<>3)&7]); + + } + /* now, the table can be loaded into the chipset */ + SMC_SELECT_BANK( 3 ); + SMC_SET_MCAST( multicast_table ); +} + +/* + . This routine will, depending on the values passed to it, + . either make it accept multicast packets, go into + . promiscuous mode ( for TCPDUMP and cousins ) or accept + . a select set of multicast packets +*/ +static void smc_set_multicast_list(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + SMC_SELECT_BANK(0); + if ( dev->flags & IFF_PROMISC ) { + PRINTK2("%s: RCR_PRMS\n", dev->name); + lp->rcr_cur_mode |= RCR_PRMS; + SMC_SET_RCR( lp->rcr_cur_mode ); + } + +/* BUG? I never disable promiscuous mode if multicasting was turned on. + Now, I turn off promiscuous mode, but I don't do anything to multicasting + when promiscuous mode is turned on. +*/ + + /* Here, I am setting this to accept all multicast packets. + I don't need to zero the multicast table, because the flag is + checked before the table is + */ + else if (dev->flags & IFF_ALLMULTI) { + lp->rcr_cur_mode |= RCR_ALMUL; + SMC_SET_RCR( lp->rcr_cur_mode ); + PRINTK2("%s: RCR_ALMUL\n", dev->name); + } + + /* We just get all multicast packets even if we only want them + . from one source. This will be changed at some future + . point. */ + else if (dev->mc_count ) { + /* support hardware multicasting */ + + /* be sure I get rid of flags I might have set */ + lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); + SMC_SET_RCR( lp->rcr_cur_mode ); + /* NOTE: this has to set the bank, so make sure it is the + last thing called. The bank is set to zero at the top */ + smc_setmulticast( ioaddr, dev->mc_count, dev->mc_list ); + } else { + PRINTK2("%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name); + lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); + SMC_SET_RCR( lp->rcr_cur_mode ); + + /* + since I'm disabling all multicast entirely, I need to + clear the multicast list + */ + SMC_SELECT_BANK( 3 ); + SMC_CLEAR_MCAST(); + } +} + + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc .. + */ +static int +smc_open(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + unsigned long ioaddr = dev->base_addr; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + /* + * Check that the address is valid. If its not, refuse + * to bring the device up. The user must specify an + * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx + */ + if (!is_valid_ether_addr(dev->dev_addr)) { + PRINTK2((KERN_DEBUG "smc_open: no valid ethernet hw addr\n")); + return -EINVAL; + } + + /* clear out all the junk that was put here before... */ + lp->saved_skb = NULL; + + // Setup the default Register Modes + lp->tcr_cur_mode = TCR_DEFAULT; + lp->rcr_cur_mode = RCR_DEFAULT; + lp->rpc_cur_mode = RPC_DEFAULT; + + /* + * If we are not using a MII interface, we need to + * monitor our own carrier signal to detect faults. + */ + if (lp->phy_type == 0) + lp->tcr_cur_mode |= TCR_MON_CSN; + + /* reset the hardware */ + smc_reset(dev); + smc_enable(dev); + + SMC_SELECT_BANK( 1 ); + SMC_SET_MAC_ADDR(dev->dev_addr); + + /* Configure the PHY */ + if (lp->phy_type != 0) + smc_phy_configure(dev); + else { + spin_lock_irq(&lp->lock); + smc_10bt_check_media(dev, 1); + spin_unlock_irq(&lp->lock); + } + + netif_start_queue(dev); + return 0; +} + +/*---------------------------------------------------- + . smc_close + . + . this makes the board clean up everything that it can + . and not talk to the outside world. Caused by + . an 'ifconfig ethX down' + . + -----------------------------------------------------*/ +static int +smc_close(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + netif_stop_queue(dev); + netif_carrier_off(dev); + + /* clear everything */ + smc_shutdown(dev->base_addr); + + spin_lock_irq(&lp->lock); + if (lp->phy_type != 0) + smc_phy_powerdown(dev, lp->mii.phy_id); + spin_unlock_irq(&lp->lock); + + return 0; +} + +/*------------------------------------------------------------ + . Get the current statistics. + . This may be called with the card open or closed. + .-------------------------------------------------------------*/ +static struct net_device_stats * +smc_query_statistics(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + + PRINTK2("%s: %s\n", dev->name, __FUNCTION__); + + return &lp->stats; +} + +/*------------------------------------------------------------ + . Ethtool support + .-------------------------------------------------------------*/ +static int +smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + int ret; + + cmd->maxtxpkt = 1; + cmd->maxrxpkt = 1; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_ethtool_gset(&lp->mii, cmd); + spin_unlock_irq(&lp->lock); + } else { + cmd->supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_TP | SUPPORTED_AUI; + + if (lp->ctl_rspeed == 10) + cmd->speed = SPEED_10; + else if (lp->ctl_rspeed == 100) + cmd->speed = SPEED_100; + + cmd->autoneg = AUTONEG_DISABLE; + cmd->transceiver = XCVR_INTERNAL; + cmd->port = 0; + cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF; + + ret = 0; + } + + return ret; +} + +static int +smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + int ret; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_ethtool_sset(&lp->mii, cmd); + spin_unlock_irq(&lp->lock); + } else { + if (cmd->autoneg != AUTONEG_DISABLE || + cmd->speed != SPEED_10 || + (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) || + (cmd->port != PORT_TP && cmd->port != PORT_AUI)) + return -EINVAL; + +// lp->port = cmd->port; + lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL; + +// if (netif_running(dev)) +// smc_set_port(dev); + + ret = 0; + } + + return ret; +} + +static void +smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) +{ + strncpy(info->driver, CARDNAME, sizeof(info->driver)); + strncpy(info->version, version, sizeof(info->version)); + strncpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info)); +} + +static int smc_ethtool_nwayreset(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + int ret = -EINVAL; + + if (lp->phy_type != 0) { + spin_lock_irq(&lp->lock); + ret = mii_nway_restart(&lp->mii); + spin_unlock_irq(&lp->lock); + } + + return ret; +} + +static u32 smc_ethtool_getmsglevel(struct net_device *dev) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + return lp->msg_enable; +} + +static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + lp->msg_enable = level; +} + +static struct ethtool_ops smc_ethtool_ops = { + .get_settings = smc_ethtool_getsettings, + .set_settings = smc_ethtool_setsettings, + .get_drvinfo = smc_ethtool_getdrvinfo, + + .get_msglevel = smc_ethtool_getmsglevel, + .set_msglevel = smc_ethtool_setmsglevel, + .nway_reset = smc_ethtool_nwayreset, + .get_link = ethtool_op_get_link, +// .get_eeprom = smc_ethtool_geteeprom, +// .set_eeprom = smc_ethtool_seteeprom, +}; + +/*---------------------------------------------------------------------- + . smc_findirq + . + . This routine has a simple purpose -- make the SMC chip generate an + . interrupt, so an auto-detect routine can detect it, and find the IRQ, + ------------------------------------------------------------------------ +*/ +int __init +smc_findirq( unsigned long ioaddr ) +{ + int timeout = 20; + unsigned long cookie; + + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__); + + cookie = probe_irq_on(); + + /* + * What I try to do here is trigger an ALLOC_INT. This is done + * by allocating a small chunk of memory, which will give an interrupt + * when done. + */ + + /* enable ALLOCation interrupts ONLY */ + SMC_SELECT_BANK(2); + SMC_SET_INT_MASK( IM_ALLOC_INT ); + + /* + . Allocate 512 bytes of memory. Note that the chip was just + . reset so all the memory is available + */ + SMC_SET_MMU_CMD( MC_ALLOC | 1 ); + + /* + . Wait until positive that the interrupt has been generated + */ + do { + int int_status; + udelay(10); + int_status = SMC_GET_INT(); + if (int_status & IM_ALLOC_INT) + break; /* got the interrupt */ + } while (--timeout); + + /* there is really nothing that I can do here if timeout fails, + as autoirq_report will return a 0 anyway, which is what I + want in this case. Plus, the clean up is needed in both + cases. */ + + /* and disable all interrupts again */ + SMC_SET_INT_MASK( 0 ); + + /* and return what I found */ + return probe_irq_off(cookie); +} + +/*---------------------------------------------------------------------- + . Function: smc_probe( unsigned long ioaddr ) + . + . Purpose: + . Tests to see if a given ioaddr points to an SMC91x chip. + . Returns a 0 on success + . + . Algorithm: + . (1) see if the high byte of BANK_SELECT is 0x33 + . (2) compare the ioaddr with the base register's address + . (3) see if I recognize the chip ID in the appropriate register + . + .--------------------------------------------------------------------- + */ +/*--------------------------------------------------------------- + . Here I do typical initialization tasks. + . + . o Initialize the structure if needed + . o print out my vanity message if not done so already + . o print out what type of hardware is detected + . o print out the ethernet address + . o find the IRQ + . o set up my private data + . o configure the dev structure with my subroutines + . o actually GRAB the irq. + . o GRAB the region + .----------------------------------------------------------------- +*/ +static int __init +smc_probe(struct net_device *dev, unsigned long ioaddr) +{ + struct smc_local *lp = (struct smc_local *)dev->priv; + static int version_printed = 0; + int i, retval; + unsigned int val, revision_register; + const char *version_string; + + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__); + +#if defined(CONFIG_ARCH_PXA_PNP2110) + /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x1010 */ + volatile unsigned char *pnp2110_mac = ioremap_nocache(0x00021000, 0x1000); + if (!pnp2110_mac) + return -ENODEV; + pnp2110_mac += 0x10; + + ioaddr = SMC_IOADDR; /* HACK ALERT!! FIXME (RSC) */ + dev->irq = SMC_IRQ; +#endif + PRINTK2("%s: ioaddr=%08x\n", CARDNAME, ioaddr); + + /* First, see if the high byte is 0x33 */ + val = SMC_CURRENT_BANK(); + PRINTK2("%s: bank signature probe returned 0x%04x\n", CARDNAME, val); + if ( (val & 0xFF00) != 0x3300 ) { + if ( (val & 0xFF) == 0x33 ) { + printk( KERN_WARNING + "%s: Detected possible byte-swapped interface" + " at IOADDR 0x%lx\n", CARDNAME, ioaddr); + } + retval = -ENODEV; + goto err_out; + } + + /* The above MIGHT indicate a device, but I need to write to further + test this. */ + SMC_SELECT_BANK(0); + val = SMC_CURRENT_BANK(); + if ( (val & 0xFF00 ) != 0x3300 ) { + retval = -ENODEV; + goto err_out; + } + + /* well, we've already written once, so hopefully another time won't + hurt. This time, I need to switch the bank register to bank 1, + so I can access the base address register */ + SMC_SELECT_BANK(1); + val = SMC_GET_BASE(); + val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; + if ( (ioaddr & ((PAGE_SIZE-1)<> 4) & 0xF]; + if (!version_string || (revision_register & 0xff00) != 0x3300) { + /* I don't recognize this chip, so... */ + printk( "%s: IO 0x%lx: Unrecognized revision register 0x%04x" + ", Contact author.\n", CARDNAME, + ioaddr, revision_register); + + retval = -ENODEV; + goto err_out; + } + + /* At this point I'll assume that the chip is an SMC91x. */ + if (version_printed++ == 0) + printk("%s", version); + + /* set the private data to zero by default */ + memset(lp, 0, sizeof(struct smc_local)); + + /* fill in some of the fields */ + dev->base_addr = ioaddr; + lp->version = revision_register & 0xff; + + /* Get the MAC address */ + SMC_SELECT_BANK( 1 ); +#if defined(CONFIG_ARCH_PXA_PNP2110) + SMC_SET_MAC_ADDR(pnp2110_mac); +#endif + SMC_GET_MAC_ADDR(dev->dev_addr); + + /* now, reset the chip, and put it into a known state */ + smc_reset( dev ); + + /* + . If dev->irq is 0, then the device has to be banged on to see + . what the IRQ is. + . + . This banging doesn't always detect the IRQ, for unknown reasons. + . a workaround is to reset the chip and try again. + . + . Interestingly, the DOS packet driver *SETS* the IRQ on the card to + . be what is requested on the command line. I don't do that, mostly + . because the card that I have uses a non-standard method of accessing + . the IRQs, and because this _should_ work in most configurations. + . + . Specifying an IRQ is done with the assumption that the user knows + . what (s)he is doing. No checking is done!!!! + . + */ + if ( dev->irq < 1 ) { + int trials; + + trials = 3; + while ( trials-- ) { + dev->irq = smc_findirq( ioaddr ); + if ( dev->irq ) + break; + /* kick the card and try again */ + smc_reset( dev ); + } + } + if (dev->irq == 0 ) { + printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n", + dev->name); + retval = -ENODEV; + goto err_out; + } + dev->irq = irq_canonicalize(dev->irq); + + /* Fill in the fields of the device structure with ethernet values. */ + ether_setup(dev); + + dev->open = smc_open; + dev->stop = smc_close; + dev->hard_start_xmit = smc_hard_start_xmit; + dev->tx_timeout = smc_timeout; + dev->watchdog_timeo = HZ/10; + dev->get_stats = smc_query_statistics; + dev->set_multicast_list = smc_set_multicast_list; + dev->ethtool_ops = &smc_ethtool_ops; + + spin_lock_init(&lp->lock); + lp->mii.phy_id_mask = 0x1f; + lp->mii.reg_num_mask = 0x1f; + lp->mii.force_media = 0; + lp->mii.full_duplex = 0; + lp->mii.dev = dev; + lp->mii.mdio_read = smc_phy_read; + lp->mii.mdio_write = smc_phy_write; + + /* + * Locate the phy, if any. + */ + if (lp->version >= (CHIP_91100 << 4)) + smc_detect_phy(dev); + + /* Set default parameters */ + lp->msg_enable = NETIF_MSG_LINK; + lp->ctl_rfduplx = 0; + lp->ctl_rspeed = 10; + +#ifndef CONFIG_ARCH_RAMSES + if (lp->version >= (CHIP_91100 << 4)) { + lp->ctl_rfduplx = 1; + lp->ctl_rspeed = 100; + } +#endif + + /* Grab the IRQ */ + retval = request_irq(dev->irq, &smc_interrupt, 0, dev->name, dev); + if (retval) + goto err_out; + +#ifdef SMC_USE_PXA_DMA + { + int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW, + smc_pxa_dma_irq, NULL); + if (dma >= 0) + dev->dma = dma; + } +#endif + + retval = register_netdev(dev); + if (retval == 0) { + /* now, print out the card info, in a short format.. */ + printk("%s: %s (rev %d) at %#lx IRQ %d", + dev->name, version_string, revision_register & 0x0f, + dev->base_addr, dev->irq); + + if (dev->dma != (unsigned char)-1) + printk(" DMA%d", dev->dma); + + printk("%s%s\n", nowait ? " [nowait]" : "", + THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); + + if (!is_valid_ether_addr(dev->dev_addr)) { + printk("%s: Invalid ethernet MAC address. Please " + "set using ifconfig\n", dev->name); + } else { + /* Print the Ethernet address */ + printk("%s: Ethernet addr: ", dev->name); + for (i = 0; i < 5; i++) + printk("%2.2x:", dev->dev_addr[i]); + printk("%2.2x\n", dev->dev_addr[5]); + } + } + +err_out: +#ifdef SMC_USE_PXA_DMA + if (retval && dev->dma != -1) + pxa_free_dma(dev->dma); +#endif + return retval; +} + +/*------------------------------------------------------------------------- + | + | smc_init( void ) + | Input parameters: + | dev->base_addr == 0, try to find all possible locations + | dev->base_addr > 0x1ff, this is the address to check + | dev->base_addr == , return failure code + | + | Output: + | 0 --> there is a device + | anything else, error + | + --------------------------------------------------------------------------- +*/ + +static int smc_enable_device(unsigned long attrib_phys) +{ + unsigned long flags; + unsigned char ecor, ecsr; + void *addr; + + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__); + + /* + * Map the attribute space. This is overkill, but clean. + */ + addr = ioremap(attrib_phys, ATTRIB_SIZE); + if (!addr) + return -ENOMEM; + + /* + * Reset the device. We must disable IRQs around this. + */ + local_irq_save(flags); + ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; + writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); + udelay(100); + + /* + * The device will ignore all writes to the enable bit while + * reset is asserted, even if the reset bit is cleared in the + * same write. Must clear reset first, then enable the device. + */ + writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); + writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); + + /* + * Set the appropriate byte/word mode. + */ + ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; +#ifndef SMC_CAN_USE_16BIT + ecsr |= ECSR_IOIS8; +#endif + writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); + local_irq_restore(flags); + + iounmap(addr); + + /* + * Wait for the chip to wake up. + */ + mdelay(1); + + return 0; +} + +static int smc_drv_probe(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev; + unsigned long base, ext_base = 0; + unsigned int *addr = NULL; + int ret = -ENODEV; + + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__); + + ndev = alloc_etherdev(sizeof(struct smc_local)); + if (!ndev) { + printk("%s: could not allocate device.\n", CARDNAME); + return -ENOMEM; + } + SET_MODULE_OWNER(ndev); + SET_NETDEV_DEV(ndev, dev); + + ndev->dma = (unsigned char)-1; + + if (pdev->num_resources < 2 || pdev->num_resources > 3) { + ret = -ENODEV; + goto out; + } + + base = pdev->resource[0].start; + ndev->irq = pdev->resource[1].start; + + /* + * Request the regions. + */ + if (!request_mem_region(base, SMC_IO_EXTENT, ndev->name)) { + ret = -EBUSY; + goto out; + } + + if (pdev->num_resources == 3) { + ext_base = pdev->resource[2].start; + + if (!request_mem_region(ext_base, ATTRIB_SIZE, ndev->name)) { + ret = -EBUSY; + goto release_1; + } + +#if defined(CONFIG_SA1100_ASSABET) + NCR_0 |= NCR_ENET_OSC_EN; +#endif + + ret = smc_enable_device(ext_base); + if (ret) + goto release_both; + } + + addr = ioremap(base, SMC_IO_EXTENT); + if (!addr) { + ret = -ENOMEM; + goto release_both; + } + + dev_set_drvdata(dev, ndev); + ret = smc_probe(ndev, (unsigned long)addr); + if (ret != 0) { + dev_set_drvdata(dev, NULL); + iounmap(addr); + release_both: + if (pdev->num_resources == 3) + release_mem_region(ext_base, ATTRIB_SIZE); + release_1: + release_mem_region(base, SMC_IO_EXTENT); + out: + printk("%s: not found (%d).\n", CARDNAME, ret); + kfree(ndev); + } + + return ret; +} + +static int smc_drv_remove(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev = dev_get_drvdata(dev); + + dev_set_drvdata(dev, NULL); + + unregister_netdev(ndev); + + free_irq(ndev->irq, ndev); + +#ifdef SMC_USE_PXA_DMA + if (ndev->dma != -1) + pxa_free_dma(ndev->dma); +#endif + iounmap((void *)ndev->base_addr); + if (pdev->num_resources == 3) + release_mem_region(pdev->resource[2].start, ATTRIB_SIZE); + release_mem_region(pdev->resource[0].start, SMC_IO_EXTENT); + + kfree(ndev); + return 0; +} + +static int smc_drv_suspend(struct device *dev, u32 state, u32 level) +{ + struct net_device *ndev = dev_get_drvdata(dev); + + if (ndev && level == SUSPEND_DISABLE) { + if (netif_running(ndev)) { + netif_device_detach(ndev); + smc_shutdown(ndev->base_addr); + } + } + return 0; +} + +static int smc_drv_resume(struct device *dev, u32 level) +{ + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev = dev_get_drvdata(dev); + + if (ndev && level == RESUME_ENABLE) { + struct smc_local *lp = (struct smc_local *)ndev->priv; + unsigned long ioaddr = ndev->base_addr; + + if (pdev->num_resources == 3) + smc_enable_device(pdev->resource[2].start); + if (netif_running(ndev)) { + smc_reset(ndev); + smc_enable(ndev); + SMC_SELECT_BANK(1); + SMC_SET_MAC_ADDR(ndev->dev_addr); + if (lp->phy_type != 0) + smc_phy_configure(ndev); + netif_device_attach(ndev); + } + } + return 0; +} + +static struct device_driver smc_driver = { + .name = CARDNAME, + .bus = &platform_bus_type, + .probe = smc_drv_probe, + .remove = smc_drv_remove, + .suspend = smc_drv_suspend, + .resume = smc_drv_resume, +}; + +static int __init smc_init(void) +{ + PRINTK2("%s: %s\n", CARDNAME, __FUNCTION__); + DEBUG_DIR(15); + DEBUG_CLR(15); + +#ifdef MODULE + if (io == -1) + printk( KERN_WARNING + "%s: You shouldn't use auto-probing with insmod!\n", + CARDNAME ); +#endif + + return driver_register(&smc_driver); +} + +static void __exit smc_cleanup(void) +{ + driver_unregister(&smc_driver); +} + +module_init(smc_init); +module_exit(smc_cleanup); diff -x .svn -urN linux-2.6.8-rc2/drivers/net/smc91x-old.h linux-2.6.8-rc2-pnp1/drivers/net/smc91x-old.h --- linux-2.6.8-rc2/drivers/net/smc91x-old.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/drivers/net/smc91x-old.h 2004-07-27 14:01:28.000000000 +0200 @@ -0,0 +1,876 @@ +/*------------------------------------------------------------------------ + . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. + . + . Copyright (C) 1996 by Erik Stahlman + . Copyright (C) 2001 Standard Microsystems Corporation + . Developed by Simple Network Magic Corporation + . Copyright (C) 2003 Monta Vista Software, Inc. + . Unified SMC91x driver by Nicolas Pitre + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . Authors + . Erik Stahlman + . Daris A Nevil + . Nicolas Pitre + . + ---------------------------------------------------------------------------*/ +#ifndef _SMC91X_H_ +#define _SMC91X_H_ + + +/* + * Define your architecture specific configuration parameters here. + */ + +#if defined(CONFIG_SA1100_GRAPHICSCLIENT) || \ + defined(CONFIG_SA1100_PFS168) || \ + defined(CONFIG_SA1100_FLEXANET) || \ + defined(CONFIG_SA1100_GRAPHICSMASTER) || \ + defined(CONFIG_ARCH_LUBBOCK) + +/* We can only do 16-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +/* The first two address lines aren't connected... */ +#define SMC_IO_SHIFT 2 + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) + +#ifdef CONFIG_ARCH_LUBBOCK +#define SMC_IOADDR LUBBOCK_ETH_PHYS +#endif + +#elif defined(CONFIG_SA1100_ASSABET) + +/* We can only do 16-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 0 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +/* The first two address lines aren't connected... */ +#define SMC_IO_SHIFT 2 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) +#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) + +#define SMC_IOADDR SA1100_CS3_PHYS + +#elif defined(CONFIG_ARCH_INNOKOM) + +#include + +/* We can only do 16-bit reads and writes in the static memory + * space. */ +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 0 + +/* The first two address lines are connected... */ +#define SMC_IO_SHIFT 0 + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) + +#define SMC_IOADDR (INNOKOM_ETH_PHYS + 0x300) +#define SMC_IRQ INNOKOM_ETH_IRQ + +#elif defined(CONFIG_ARCH_MAINSTONE) || defined(CONFIG_ARCH_PXA_IDP) || defined(CONFIG_ARCH_RAMSES) + +#ifdef CONFIG_ARCH_MAINSTONE +#include +#define SMC_IOADDR (MST_ETH_PHYS + 0x300) +#define SMC_IRQ MAINSTONE_IRQ(3) + +#elif CONFIG_ARCH_PXA_IDP +#include +#define SMC_IOADDR (IDP_ETH_PHYS + 0x300) +#define SMC_IRQ ETHERNET_IRQ + +#elif CONFIG_ARCH_RAMSES +#include +#define SMC_IOADDR (RAMSES_ETH_PHYS + 0x300) +#define SMC_IRQ ETHERNET_IRQ +#endif + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 1 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 +#define SMC_USE_PXA_DMA 1 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) +#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) + +/* We actually can't write halfwords properly if not word aligned */ +static inline void +SMC_outw(u16 val, unsigned long ioaddr, int reg) +{ + if (reg & 2) { + unsigned int v = val << 16; + v |= readl(ioaddr + (reg & ~2)) & 0xffff; + writel(v, ioaddr + (reg & ~2)); + } else { + writew(val, ioaddr + reg); + } +} + +#elif defined(CONFIG_ARCH_PXA_PNP2110) + +#include +#define SMC_IOADDR (PNP2110_ETH_VIRT + 0x300) +#define SMC_IRQ (PNP2110_ETH_IRQ) + +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 0 +#undef SMC_USE_PXA_DMA +//#define SMC_USE_PXA_DMA 1 +#ifdef CONFIG_ARM_SMC91X_TX_DMA +#define SMC_USE_PXA_DMA_TX 1 +#else +#define SMC_USE_PXA_DMA_TX 0 +#endif + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) + +#elif defined(CONFIG_ISA) + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 + +#define SMC_inb(a, r) inb((a) + (r)) +#define SMC_inw(a, r) inw((a) + (r)) +#define SMC_outb(v, a, r) outb(v, (a) + (r)) +#define SMC_outw(v, a, r) outw(v, (a) + (r)) +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#else + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 1 +#define SMC_NOWAIT 1 + +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) +#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) + +#endif + + +#ifdef SMC_USE_PXA_DMA +/* + * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is + * always happening in irq context so no need to worry about races. TX is + * different and probably not worth it for that reason, and not as critical + * as RX which can overrun memory and lose packets. + */ +#include +#include + +#ifdef SMC_insl +#undef SMC_insl +#define SMC_insl(a, r, p, l) smc_pxa_dma_insl(a, r, dev->dma, p, l) +static inline void +smc_pxa_dma_insl(u_long ioaddr, int reg, int dma, u_char *buf, int len) +{ + dma_addr_t dmabuf; + + /* fallback if no DMA available */ + if (dma == -1) { + insl(ioaddr + reg, buf, len); + return; + } + + /* 64 bit alignment is required for memory to memory DMA */ + if ((long)buf & 4) { + *((u32 *)buf)++ = SMC_inl(ioaddr, reg); + len--; + } + + len *= 4; + dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE); + DCSR(dma) = DCSR_NODESC; + DTADR(dma) = dmabuf; + DSADR(dma) = SMC_IOADDR + reg; + DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | + DCMD_WIDTH4 | (DCMD_LENGTH & len)); + DCSR(dma) = DCSR_NODESC | DCSR_RUN; + while (!(DCSR(dma) & DCSR_STOPSTATE)); + DCSR(dma) = 0; + dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE); +} +#endif + +#ifdef SMC_insw +#undef SMC_insw +#define SMC_insw(a, r, p, l) smc_pxa_dma_insw(a, r, dev->dma, p, l) +static inline void +smc_pxa_dma_insw(u_long ioaddr, int reg, int dma, u_char *buf, int len) +{ + dma_addr_t dmabuf; + + /* fallback if no DMA available */ + if (dma == -1) { + insw(ioaddr + reg, buf, len); + return; + } + + /* 64 bit alignment is required for memory to memory DMA */ + while ((long)buf & 6) { + *((u16 *)buf)++ = SMC_inw(ioaddr, reg); + len--; + } + + len *= 2; + dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE); + DCSR(dma) = DCSR_NODESC; + DTADR(dma) = dmabuf; + DSADR(dma) = SMC_IOADDR + reg; + DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | + DCMD_WIDTH2 | (DCMD_LENGTH & len)); + DCSR(dma) = DCSR_NODESC | DCSR_RUN; + while (!(DCSR(dma) & DCSR_STOPSTATE)); + DCSR(dma) = 0; + dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE); +} +#endif + +static void +smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs) +{ + DCSR(dma) = 0; +} +#endif /* SMC_USE_PXA_DMA */ + + +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ +#ifndef SMC_IO_SHIFT +#define SMC_IO_SHIFT 0 +#endif +#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) + + +/* + . Bank Select Register: + . + . yyyy yyyy 0000 00xx + . xx = bank number + . yyyy yyyy = 0x33, for identification purposes. +*/ +#define BANK_SELECT (14 << SMC_IO_SHIFT) + + +// Transmit Control Register +/* BANK 0 */ +#define TCR_REG SMC_REG(0x0000, 0) +#define TCR_ENABLE 0x0001 // When 1 we can transmit +#define TCR_LOOP 0x0002 // Controls output pin LBK +#define TCR_FORCOL 0x0004 // When 1 will force a collision +#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 +#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames +#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier +#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation +#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error +#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback +#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode + +#define TCR_CLEAR 0 /* do NOTHING */ +/* the default settings for the TCR register : */ +#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) + + +// EPH Status Register +/* BANK 0 */ +#define EPH_STATUS_REG SMC_REG(0x0002, 0) +#define ES_TX_SUC 0x0001 // Last TX was successful +#define ES_SNGL_COL 0x0002 // Single collision detected for last tx +#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx +#define ES_LTX_MULT 0x0008 // Last tx was a multicast +#define ES_16COL 0x0010 // 16 Collisions Reached +#define ES_SQET 0x0020 // Signal Quality Error Test +#define ES_LTXBRD 0x0040 // Last tx was a broadcast +#define ES_TXDEFR 0x0080 // Transmit Deferred +#define ES_LATCOL 0x0200 // Late collision detected on last tx +#define ES_LOSTCARR 0x0400 // Lost Carrier Sense +#define ES_EXC_DEF 0x0800 // Excessive Deferral +#define ES_CTR_ROL 0x1000 // Counter Roll Over indication +#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin +#define ES_TXUNRN 0x8000 // Tx Underrun + + +// Receive Control Register +/* BANK 0 */ +#define RCR_REG SMC_REG(0x0004, 0) +#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted +#define RCR_PRMS 0x0002 // Enable promiscuous mode +#define RCR_ALMUL 0x0004 // When set accepts all multicast frames +#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets +#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets +#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision +#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier +#define RCR_SOFTRST 0x8000 // resets the chip + +/* the normal settings for the RCR register : */ +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) +#define RCR_CLEAR 0x0 // set it to a base state + + +// Counter Register +/* BANK 0 */ +#define COUNTER_REG SMC_REG(0x0006, 0) + + +// Memory Information Register +/* BANK 0 */ +#define MIR_REG SMC_REG(0x0008, 0) + + +// Receive/Phy Control Register +/* BANK 0 */ +#define RPC_REG SMC_REG(0x000A, 0) +#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. +#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode +#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode +#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb +#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb +#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect +#define RPC_LED_RES (0x01) // LED = Reserved +#define RPC_LED_10 (0x02) // LED = 10Mbps link detect +#define RPC_LED_FD (0x03) // LED = Full Duplex Mode +#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred +#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect +#define RPC_LED_TX (0x06) // LED = TX packet occurred +#define RPC_LED_RX (0x07) // LED = RX packet occurred +#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) + + +/* Bank 0 0x0C is reserved */ + +// Bank Select Register +/* All Banks */ +#define BSR_REG 0x000E + + +// Configuration Reg +/* BANK 1 */ +#define CONFIG_REG SMC_REG(0x0000, 1) +#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy +#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL +#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus +#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. + +// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low +#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) + + +// Base Address Register +/* BANK 1 */ +#define BASE_REG SMC_REG(0x0002, 1) + + +// Individual Address Registers +/* BANK 1 */ +#define ADDR0_REG SMC_REG(0x0004, 1) +#define ADDR1_REG SMC_REG(0x0006, 1) +#define ADDR2_REG SMC_REG(0x0008, 1) + + +// General Purpose Register +/* BANK 1 */ +#define GP_REG SMC_REG(0x000A, 1) + + +// Control Register +/* BANK 1 */ +#define CTL_REG SMC_REG(0x000C, 1) +#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received +#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically +#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt +#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt +#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt +#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store +#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers +#define CTL_STORE 0x0001 // When set stores registers into EEPROM + + +// MMU Command Register +/* BANK 2 */ +#define MMU_CMD_REG SMC_REG(0x0000, 2) +#define MC_BUSY 1 // When 1 the last release has not completed +#define MC_NOP (0<<5) // No Op +#define MC_ALLOC (1<<5) // OR with number of 256 byte packets +#define MC_RESET (2<<5) // Reset MMU to initial state +#define MC_REMOVE (3<<5) // Remove the current rx packet +#define MC_RELEASE (4<<5) // Remove and release the current rx packet +#define MC_FREEPKT (5<<5) // Release packet in PNR register +#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit +#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs + + +// Packet Number Register +/* BANK 2 */ +#define PN_REG SMC_REG(0x0002, 2) + + +// Allocation Result Register +/* BANK 2 */ +#define AR_REG SMC_REG(0x0003, 2) +#define AR_FAILED 0x80 // Alocation Failed + + +// TX FIFO Ports Register +/* BANK 2 */ +#define TXFIFO_REG SMC_REG(0x0004, 2) +#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty + +// RX FIFO Ports Register +/* BANK 2 */ +#define RXFIFO_REG SMC_REG(0x0005, 2) +#define RXFIFO_REMPTY 0x80 // RX FIFO Empty + +#define FIFO_REG SMC_REG(0x0004, 2) + +// Pointer Register +/* BANK 2 */ +#define PTR_REG SMC_REG(0x0006, 2) +#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area +#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access +#define PTR_READ 0x2000 // When 1 the operation is a read + + +// Data Register +/* BANK 2 */ +#define DATA_REG SMC_REG(0x0008, 2) + + +// Interrupt Status/Acknowledge Register +/* BANK 2 */ +#define INT_REG SMC_REG(0x000C, 2) + + +// Interrupt Mask Register +/* BANK 2 */ +#define IM_REG SMC_REG(0x000D, 2) +#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt +#define IM_ERCV_INT 0x40 // Early Receive Interrupt +#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section +#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns +#define IM_ALLOC_INT 0x08 // Set when allocation request is completed +#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty +#define IM_TX_INT 0x02 // Transmit Interrupt +#define IM_RCV_INT 0x01 // Receive Interrupt + + +// Multicast Table Registers +/* BANK 3 */ +#define MCAST_REG1 SMC_REG(0x0000, 3) +#define MCAST_REG2 SMC_REG(0x0002, 3) +#define MCAST_REG3 SMC_REG(0x0004, 3) +#define MCAST_REG4 SMC_REG(0x0006, 3) + + +// Management Interface Register (MII) +/* BANK 3 */ +#define MII_REG SMC_REG(0x0008, 3) +#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup +#define MII_MDOE 0x0008 // MII Output Enable +#define MII_MCLK 0x0004 // MII Clock, pin MDCLK +#define MII_MDI 0x0002 // MII Input, pin MDI +#define MII_MDO 0x0001 // MII Output, pin MDO + + +// Revision Register +/* BANK 3 */ +/* ( hi: chip id low: rev # ) */ +#define REV_REG SMC_REG(0x000A, 3) + + +// Early RCV Register +/* BANK 3 */ +/* this is NOT on SMC9192 */ +#define ERCV_REG SMC_REG(0x000C, 3) +#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received +#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask + + +// External Register +/* BANK 7 */ +#define EXT_REG SMC_REG(0x0000, 7) + + +#define CHIP_9192 3 +#define CHIP_9194 4 +#define CHIP_9195 5 +#define CHIP_9196 6 +#define CHIP_91100 7 +#define CHIP_91100FD 8 +#define CHIP_91111FD 9 + +static const char * chip_ids[ 16 ] = { + NULL, NULL, NULL, + /* 3 */ "SMC91C90/91C92", + /* 4 */ "SMC91C94", + /* 5 */ "SMC91C95", + /* 6 */ "SMC91C96", + /* 7 */ "SMC91C100", + /* 8 */ "SMC91C100FD", + /* 9 */ "SMC91C11xFD", + NULL, NULL, NULL, + NULL, NULL, NULL}; + + +/* + . Transmit status bits +*/ +#define TS_SUCCESS 0x0001 +#define TS_LOSTCAR 0x0400 +#define TS_LATCOL 0x0200 +#define TS_16COL 0x0010 + +/* + . Receive status bits +*/ +#define RS_ALGNERR 0x8000 +#define RS_BRODCAST 0x4000 +#define RS_BADCRC 0x2000 +#define RS_ODDFRAME 0x1000 +#define RS_TOOLONG 0x0800 +#define RS_TOOSHORT 0x0400 +#define RS_MULTICAST 0x0001 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) + + +/* + * PHY IDs + * LAN83C183 == LAN91C111 Internal PHY + */ +#define PHY_LAN83C183 0x0016f840 +#define PHY_LAN83C180 0x02821c50 + +/* + * PHY Register Addresses (LAN91C111 Internal PHY) + * + * Generic PHY registers can be found in + * + * These phy registers are specific to our on-board phy. + */ + +// PHY Configuration Register 1 +#define PHY_CFG1_REG 0x10 +#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled +#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled +#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down +#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler +#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable +#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled +#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) +#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db +#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time + + +// PHY Configuration Register 2 +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled +#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled +#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) +#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo + +// PHY Status Output (and Interrupt status) Register +#define PHY_INT_REG 0x12 // Status Output (Interrupt Status) +#define PHY_INT_INT 0x8000 // 1=bits have changed since last read +#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected +#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync +#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx +#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx +#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx +#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected +#define PHY_INT_JAB 0x0100 // 1=Jabber detected +#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode +#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex + +// PHY Interrupt/Status Mask Register +#define PHY_MASK_REG 0x13 // Interrupt Mask +// Uses the same bit definitions as PHY_INT_REG + + +/* + * SMC91C96 ethernet config and status registers. + * These are in the "attribute" space. + */ +#define ECOR 0x8000 +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x04 +#define ECOR_ENABLE 0x01 + +#define ECSR 0x8002 +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 + +#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) + + +/* + * Macros to abstract register access according to the data bus + * capabilities. Please try to use those and not the in/out primitives. + * Note: the following macros do *not* select the bank -- this must + * be done separately as needed in the main code. The SMC_REG() macro + * only uses the bank argument for debugging purposes. + */ + +#if SMC_DEBUG > 0 +#define SMC_REG(reg, bank) \ + ({ \ + int __b = SMC_CURRENT_BANK(); \ + if ((__b & ~0xf0) != (0x3300 | bank)) { \ + printk( "%s: bank reg screwed (0x%04x)\n", \ + CARDNAME, __b ); \ + BUG(); \ + } \ + reg<> 8) +#define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF) +#define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8) +#define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF) +#define SMC_ACK_INT(x) \ + do { \ + unsigned long __flags; \ + int __mask; \ + local_irq_save(__flags); \ + __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ + SMC_outw( __mask | (x), ioaddr, INT_REG ); \ + local_irq_restore(__flags); \ + } while (0) +#define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8) +#define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG ) +#endif + +#define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT ) +#define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT ) +#define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG ) +#define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG ) +#define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG ) +#define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG ) +#define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG ) +#define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG ) +#define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG ) +#define SMC_GET_MII() SMC_inw( ioaddr, MII_REG ) +#define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG ) +#define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG ) +#define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG ) +#define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG ) +#define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG ) +#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG ) +#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG ) +#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG ) +#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG ) +#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG ) +#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG ) +#define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG ) +#define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG ) +#define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG ) +#define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG ) + +#ifndef SMC_GET_MAC_ADDR +#define SMC_GET_MAC_ADDR(addr) \ + do { \ + unsigned int __v; \ + __v = SMC_inw( ioaddr, ADDR0_REG ); \ + addr[0] = __v; addr[1] = __v >> 8; \ + __v = SMC_inw( ioaddr, ADDR1_REG ); \ + addr[2] = __v; addr[3] = __v >> 8; \ + __v = SMC_inw( ioaddr, ADDR2_REG ); \ + addr[4] = __v; addr[5] = __v >> 8; \ + } while (0) +#endif + +#define SMC_SET_MAC_ADDR(addr) \ + do { \ + SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ + SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ + SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ + } while (0) + +#define SMC_CLEAR_MCAST() \ + do { \ + SMC_outw( 0, ioaddr, MCAST_REG1 ); \ + SMC_outw( 0, ioaddr, MCAST_REG2 ); \ + SMC_outw( 0, ioaddr, MCAST_REG3 ); \ + SMC_outw( 0, ioaddr, MCAST_REG4 ); \ + } while (0) +#define SMC_SET_MCAST(x) \ + do { \ + unsigned char *mt = (x); \ + SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ + SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ + SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ + SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ + } while (0) + +#if SMC_CAN_USE_32BIT +/* + * Some setups just can't write 8 or 16 bits reliably when not aligned + * to a 32 bit boundary. I tell you that exists! + * We do the ones that can have their low parts written to 0 here. + */ +#undef SMC_SELECT_BANK +#define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<> 16; \ + } while (0) +#else +#define SMC_PUT_PKT_HDR(status, length) \ + do { \ + SMC_outw( status, ioaddr, DATA_REG ); \ + SMC_outw( length, ioaddr, DATA_REG ); \ + } while (0) +#define SMC_GET_PKT_HDR(status, length) \ + do { \ + (status) = SMC_inw( ioaddr, DATA_REG ); \ + (length) = SMC_inw( ioaddr, DATA_REG ); \ + } while (0) +#endif + +#if SMC_CAN_USE_32BIT +#define SMC_PUSH_DATA(p, l) \ + do { \ + char *__ptr = (p); \ + int __len = (l); \ + if (__len >= 2 && (long)__ptr & 2) { \ + __len -= 2; \ + SMC_outw( *((u16 *)__ptr)++, ioaddr, DATA_REG );\ + } \ + SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \ + if (__len & 2) { \ + __ptr += (__len & ~3); \ + SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ + } \ + } while (0) +#define SMC_PULL_DATA(p, l) \ + do { \ + char *__ptr = (p); \ + int __len = (l); \ + if ((long)__ptr & 2) { \ + /* \ + * We want 32bit alignment here. \ + * Since some buses perform a full 32bit \ + * fetch even for 16bit data we can't use \ + * SMC_inw() here. Back both source (on chip \ + * and destination) pointers of 2 bytes. \ + */ \ + (long)__ptr &= ~2; \ + __len += 2; \ + SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \ + } \ + __len += 2; \ + SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \ + } while (0) +#elif SMC_CAN_USE_16BIT +#define SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 ) +#define SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 ) +#elif SMC_CAN_USE_8BIT +#define SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l ) +#define SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l ) +#endif + +#if ! SMC_CAN_USE_16BIT +#define SMC_outw(x, ioaddr, reg) \ + do { \ + unsigned int __val16 = (x); \ + SMC_outb( __val16, ioaddr, reg ); \ + SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ + } while (0) +#define SMC_inw(ioaddr, reg) \ + ({ \ + unsigned int __val16; \ + __val16 = SMC_inb( ioaddr, reg ); \ + __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ + __val16; \ + }) +#endif + + +#endif /* _SMC91X_H_ */ diff -x .svn -urN linux-2.6.8-rc2/include/asm-arm/arch-pxa/csb226.h linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/csb226.h --- linux-2.6.8-rc2/include/asm-arm/arch-pxa/csb226.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/csb226.h 2004-07-27 13:57:20.000000000 +0200 @@ -0,0 +1,48 @@ +/* + * linux/include/asm-arm/arch-pxa/csb226.h + * + * (c) 2003 Robert Schwebel , Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _INCLUDE_ASMARM_ARCHPXA_CSB226_H_ +#define _INCLUDE_ASMARM_ARCHPXA_CSB226_H_ + +/* + * GPIOs + */ +#define GPIO_CSB226_ETH 14 + +/* + * ethernet chip (CS8900) + */ +#define CSB226_ETH_PHYS PXA_CS2_PHYS /* 0x08000000 */ +#define CSB226_ETH_VIRT (0xf8000000) +#define CSB226_ETH_SIZE (1*1024*1024) +#define CSB226_ETH_IRQ IRQ_GPIO(GPIO_CSB226_ETH) +#define CSB226_ETH_IRQ_EDGE GPIO_RISING_EDGE + +/* + * USB disconnect interrupt & USB on/off GPIO + */ +#define GPIO_CSB226_USB_DISC 42 /* USB disconnect */ +#define GPIO_CSB226_USB_ONOFF 45 /* switch on/off USB pullup */ +#define CSB226_USB_DISC_IRQ IRQ_GPIO(GPIO_CSB226_USB_DISC) +#define CSB226_USB_DISC_IRQ_EDGE IRQT_RISING + +/* + * virtual to physical conversion macros + */ +#define CSB226_P2V(x) ((x) - CSB226_FPGA_PHYS + CSB226_FPGA_VIRT) +#define CSB226_V2P(x) ((x) - CSB226_FPGA_VIRT + CSB226_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __CSB226_REG(x) (*((volatile unsigned long *)CSB226_P2V(x))) +#else +# define __CSB226_REG(x) CSB226_P2V(x) +#endif + +#endif diff -x .svn -urN linux-2.6.8-rc2/include/asm-arm/arch-pxa/fpbus.h linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/fpbus.h --- linux-2.6.8-rc2/include/asm-arm/arch-pxa/fpbus.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/fpbus.h 2004-07-27 13:57:20.000000000 +0200 @@ -0,0 +1,29 @@ +/* + * include/asm-arm/arch-pxa/fpbus.h + * + * (C) Copyright 2004 Robert Schwebel, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_FPBUS +#define __ASM_ARCH_FPBUS + +/* + * NGE Testboard 2 + */ + +#ifdef CONFIG_FPBUS_NGE_TB2 +#undef FPBUS_MSEL0 +#undef FPBUS_MSEL1 +#define FPBUS_DATA0 58 +#define FPBUS_DCLK 59 +#define FPBUS_CONF_DONE 61 +#define FPBUS_NCONFIG 62 +#define FPBUS_NSTATUS 60 +#endif + + +#endif /* __ASM_ARCH_FPBUS */ diff -x .svn -urN linux-2.6.8-rc2/include/asm-arm/arch-pxa/gpio.h linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/gpio.h --- linux-2.6.8-rc2/include/asm-arm/arch-pxa/gpio.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/gpio.h 2004-07-27 13:57:20.000000000 +0200 @@ -0,0 +1,49 @@ +/* + * linux/include/asm-arm/arch-pxa/gpio.h + * + * Copyright (C) 2004 Robert Schwebel, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARM_PXA_GPIO_H +#define __ARM_PXA_GPIO_H + +#include +#include + +#define DEBUG 1 + +static inline void gpio_set_pin(int gpio_nr) +{ + GPSR(gpio_nr) |= GPIO_bit(gpio_nr); + return; +} + +static inline void gpio_clear_pin(int gpio_nr) +{ + GPCR(gpio_nr) |= GPIO_bit(gpio_nr); + return; +} + +static inline void gpio_dir_input(int gpio_nr) +{ + GPDR(gpio_nr) &= ~GPIO_bit(gpio_nr); + return; +} + +static inline void gpio_dir_output(int gpio_nr) +{ + GPDR(gpio_nr) |= GPIO_bit(gpio_nr); + return; +} + +static inline int gpio_get_pin(int gpio_nr) +{ + return GPLR(gpio_nr) & GPIO_bit(gpio_nr); +} + + +#endif diff -x .svn -urN linux-2.6.8-rc2/include/asm-arm/arch-pxa/i2c-pxa.h linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/i2c-pxa.h --- linux-2.6.8-rc2/include/asm-arm/arch-pxa/i2c-pxa.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/i2c-pxa.h 2004-07-27 13:57:20.000000000 +0200 @@ -0,0 +1,76 @@ +/* + * i2c_pxa.h + * + * Copyright (C) 2002 Intrinsyc Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _I2C_PXA_H_ +#define _I2C_PXA_H_ + +struct i2c_algo_pxa_data +{ + void (*write_byte) (u8 value); + u8 (*read_byte) (void); + void (*start) (void); + void (*repeat_start) (void); + void (*stop) (void); + void (*abort) (void); + int (*wait_bus_not_busy) (void); + int (*wait_for_interrupt) (int wait_type); + void (*transfer) (int lastbyte, int receive, int midbyte); + void (*reset) (void); + + int udelay; + int timeout; +}; + +#define DEF_TIMEOUT 3 +#define BUS_ERROR (-EREMOTEIO) +#define ACK_DELAY 0 /* time to delay before checking bus error */ +#define MAX_MESSAGES 65536 /* maximum number of messages to send */ + +#define I2C_SLEEP_TIMEOUT 2 /* time to sleep for on i2c transactions */ +#define I2C_RETRY (-2000) /* an error has occurred retry transmit */ +#define I2C_TRANSMIT 1 +#define I2C_RECEIVE 0 +#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) /* ICR initialization value */ +/* ICR initialize bit values +* +* 15. FM 0 (100 Khz operation) +* 14. UR 0 (No unit reset) +* 13. SADIE 0 (Disables the unit from interrupting on slave addresses +* matching its slave address) +* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration +* in master mode) +* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode) +* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent) +* 9. IRFIE 1 (Enable interrupts from full buffer received) +* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty) +* 7. GCD 1 (Disables i2c unit response to general call messages as a slave) +* 6. IUE 0 (Disable unit until we change settings) +* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL) +* 4. MA 0 (Only send stop with the ICR stop bit) +* 3. TB 0 (We are not transmitting a byte initially) +* 2. ACKNAK 0 (Send an ACK after the unit receives a byte) +* 1. STOP 0 (Do not send a STOP) +* 0. START 0 (Do not send a START) +* +*/ + +#define I2C_ISR_INIT 0x7FF /* status register init */ +/* I2C status register init values + * + * 10. BED 1 (Clear bus error detected) + * 9. SAD 1 (Clear slave address detected) + * 7. IRF 1 (Clear IDBR Receive Full) + * 6. ITE 1 (Clear IDBR Transmit Empty) + * 5. ALD 1 (Clear Arbitration Loss Detected) + * 4. SSD 1 (Clear Slave Stop Detected) + */ + +#endif diff -x .svn -urN linux-2.6.8-rc2/include/asm-arm/arch-pxa/innokom.h linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/innokom.h --- linux-2.6.8-rc2/include/asm-arm/arch-pxa/innokom.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/innokom.h 2004-07-27 13:57:20.000000000 +0200 @@ -0,0 +1,68 @@ +/* + * linux/include/asm-arm/arch-pxa/innokom.h + * + * (c) 2003 Robert Schwebel , Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _INCLUDE_ASMARM_ARCHPXA_INNOKOM_H_ +#define _INCLUDE_ASMARM_ARCHPXA_INNOKOM_H_ + +/* + * SW Update Button + */ +#define GPIO_INNOKOM_SW_UPDATE 11 +#define INNOKOM_SW_UPDATE_IRQ IRQ_GPIO(GPIO_INNOKOM_SW_UPDATE) +#define INNOKOM_SW_UPDATE_IRQ_EDGE IRQT_FALLING + +/* + * Reset Button + */ +#define GPIO_INNOKOM_RESET 3 +#define INNOKOM_RESET_IRQ IRQ_GPIO(GPIO_INNOKOM_RESET) +#define INNOKOM_RESET_IRQ_EDGE IRQT_FALLING + +/* + * ethernet chip (SMSC91C111) + */ +#define GPIO_INNOKOM_ETH 59 +#define INNOKOM_ETH_PHYS PXA_CS5_PHYS /* phys 0x14000000 */ +#define INNOKOM_ETH_VIRT (0xf0000000) +#define INNOKOM_ETH_SIZE (1*1024*1024) +#define INNOKOM_ETH_IRQ IRQ_GPIO(GPIO_INNOKOM_ETH) +#define INNOKOM_ETH_IRQ_EDGE IRQT_RISING + +/* + * USB disconnect interrupt & USB on/off GPIO + */ +#define GPIO_INNOKOM_USB_DISC 42 /* USB disconnect */ +#define GPIO_INNOKOM_USB_ONOFF 45 /* switch on/off USB pullup */ +#define INNOKOM_USB_DISC_IRQ IRQ_GPIO(GPIO_INNOKOM_USB_DISC) +#define INNOKOM_USB_DISC_IRQ_EDGE IRQT_RISING + +/* + * virtual to physical conversion macros + */ +#define INNOKOM_P2V(x) ((x) - INNOKOM_FPGA_PHYS + INNOKOM_FPGA_VIRT) +#define INNOKOM_V2P(x) ((x) - INNOKOM_FPGA_VIRT + INNOKOM_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __INNOKOM_REG(x) (*((volatile unsigned long *)INNOKOM_P2V(x))) +#else +# define __INNOKOM_REG(x) INNOKOM_P2V(x) +#endif + +#endif diff -x .svn -urN linux-2.6.8-rc2/include/asm-arm/arch-pxa/pnp2110.h linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/pnp2110.h --- linux-2.6.8-rc2/include/asm-arm/arch-pxa/pnp2110.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/pnp2110.h 2004-07-27 13:57:20.000000000 +0200 @@ -0,0 +1,47 @@ +/* + * linux/include/asm-arm/arch-pxa/pnp2110.h + * + * (c) 2004 Robert Schwebel , Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _INCLUDE_ASMARM_ARCHPXA_PNP2110_H_ +#define _INCLUDE_ASMARM_ARCHPXA_PHP2110_H_ + +/* + * Ethernet chip (SMSC91C111) + */ + +#define GPIO_PNP2110_ETH 0 +#define PNP2110_10_ETH_PHYS (0x2C000300) /* Rev. 1.0: 0x2C000300 */ +#define PNP2110_20_ETH_PHYS (PXA_CS1_PHYS+0x0300) /* Rev. 2.0: 0x04000300 */ +#define PNP2110_ETH_SIZE (0x1000) +#define PNP2110_ETH_IRQ IRQ_GPIO(GPIO_PNP2110_ETH) +#define PNP2110_ETH_IRQ_EDGE IRQT_RISING + +/* + * virtual to physical conversion macros + */ +#define PNP2110_P2V(x) ((x) - PNP2110_FPGA_PHYS + PNP2110_FPGA_VIRT) +#define PNP2110_V2P(x) ((x) - PNP2110_FPGA_VIRT + PNP2110_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __PNP2110_REG(x) (*((volatile unsigned long *)PNP2110_P2V(x))) +#else +# define __PNP2110_REG(x) PNP2110_P2V(x) +#endif + +#endif diff -x .svn -urN linux-2.6.8-rc2/include/asm-arm/arch-pxa/system.h linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/system.h --- linux-2.6.8-rc2/include/asm-arm/arch-pxa/system.h 2004-06-16 07:19:13.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/system.h 2004-07-27 13:57:21.000000000 +0200 @@ -10,8 +10,13 @@ * published by the Free Software Foundation. */ +#ifndef __SYSTEM_H +#define __SYSTEM_H + #include "hardware.h" +extern void printascii(const char *); + static inline void arch_idle(void) { cpu_do_idle(); @@ -31,3 +36,4 @@ } } +#endif /* __SYSTEM_H */ diff -x .svn -urN linux-2.6.8-rc2/include/asm-arm/arch-pxa/trizeps2.h linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/trizeps2.h --- linux-2.6.8-rc2/include/asm-arm/arch-pxa/trizeps2.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/asm-arm/arch-pxa/trizeps2.h 2004-07-27 13:57:21.000000000 +0200 @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/arch-pxa/trizeps2.h + * + * (c) 2004 Robert Schwebel , Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _INCLUDE_ASMARM_ARCHPXA_TRIZEPS2_H_ +#define _INCLUDE_ASMARM_ARCHPXA_TRIZEPS2_H_ + +/* + * virtual to physical conversion macros + */ +#define TRIZEPS2_P2V(x) ((x) - TRIZEPS2_FPGA_PHYS + TRIZEPS2_FPGA_VIRT) +#define TRIZEPS2_V2P(x) ((x) - TRIZEPS2_FPGA_VIRT + TRIZEPS2_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __TRIZEPS2_REG(x) (*((volatile unsigned long *)TRIZEPS2_P2V(x))) +#else +# define __TRIZEPS2_REG(x) TRIZEPS2_P2V(x) +#endif + +#endif diff -x .svn -urN linux-2.6.8-rc2/include/linux/fpbus.h linux-2.6.8-rc2-pnp1/include/linux/fpbus.h --- linux-2.6.8-rc2/include/linux/fpbus.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/linux/fpbus.h 2004-07-27 13:57:25.000000000 +0200 @@ -0,0 +1,70 @@ +/* + * fpbus_fpga.h + * + */ + +#ifndef __FPBUS_H +#define __FPBUS_H + +#include + +struct fpbus_dev +{ + struct device dev; +}; + +#define to_fpbus_dev(n) container_of(n, struct fpbus_dev, dev) + +/* + * The config space of the FPGAs starts with a tagged list. + * This definition follows the definition as of protocol-20040604-1. + */ + +#define FTAG_CORE 0x50494900 +struct ftag_core { + u32 tag_type; + u32 firmware_revision[4]; /* material number: "FE/xxxxxx/xxxx" (x numerical) */ + u32 version_number; /* continiously incremented per version */ + u32 compile_date; /* compile date/time (TBD: format?) */ + u32 timing_cs3; /* ? TBD */ + u32 timing_cs4; /* ? TBD */ + u32 dummy[2]; /* for future extensions */ +}; + +#define FTAG_DEV 0x50494901 +struct ftag_dev { + u32 tag_type; + u32 dev_id; /* identifies hardware device (IP) */ + u32 dev_sub_id; /* for devices that need more than one mem window */ + u16 interface_revision; /* hw/sw interface */ + u16 ip_revision; /* internal IP revision, without interface change */ + u32 base_address; /* start of IP device, physical address */ + u32 size; /* starting at base_address */ + u32 dummy[2]; /* for future extensions */ +}; + +#define FTAG_END 0x50494902 +struct ftag_end { + u32 tag_type; +}; + +struct ftag_tag { + u32 tag_type; +}; + +union ftag { + struct ftag_core core; + struct ftag_dev dev; + struct ftag_end end; + struct ftag_tag tag; +}; + +/* for chip drivers */ +struct fpbus_ops { + int(*fpbus_init_device)(const struct firmware *fw); +}; + +int fpbus_register(struct fpbus_ops *ops); +void fpbus_unregister(struct fpbus_ops *ops); + +#endif /* __FPBUS_H */ diff -x .svn -urN linux-2.6.8-rc2/include/linux/gpio.h linux-2.6.8-rc2-pnp1/include/linux/gpio.h --- linux-2.6.8-rc2/include/linux/gpio.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/include/linux/gpio.h 2004-07-27 13:57:35.000000000 +0200 @@ -0,0 +1,27 @@ +/* + * include/linux/gpio.h + * + * Copyright (C) 2004 Robert Schwebel, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __GPIO_H +#define __GPIO_H + +#include "asm/arch/gpio.h" + +/* Values for policy */ +#define GPIO_KERNEL (1<<0) +#define GPIO_USER (1<<1) +#define GPIO_INPUT (1<<2) +#define GPIO_OUTPUT (1<<3) + +int request_gpio(unsigned int pin_nr, const char *owner, + unsigned char policy, unsigned char init_level); + +void free_gpio(unsigned int pin_nr); + +#endif diff -x .svn -urN linux-2.6.8-rc2/include/linux/i2c-id.h linux-2.6.8-rc2-pnp1/include/linux/i2c-id.h --- linux-2.6.8-rc2/include/linux/i2c-id.h 2004-07-27 14:08:08.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/include/linux/i2c-id.h 2004-07-27 13:57:31.000000000 +0200 @@ -195,6 +195,7 @@ #define I2C_ALGO_BITHS 0x130000 /* enhanced bit style adapters */ #define I2C_ALGO_OCP_IOP3XX 0x140000 /* XSCALE IOP3XX On-chip I2C alg */ +#define I2C_ALGO_PXA 0x200000 /* Intel PXA I2C algorithm */ #define I2C_ALGO_EXP 0x800000 /* experimental */ #define I2C_ALGO_MASK 0xff0000 /* Mask for algorithms */ diff -x .svn -urN linux-2.6.8-rc2/init/Kconfig linux-2.6.8-rc2-pnp1/init/Kconfig --- linux-2.6.8-rc2/init/Kconfig 2004-07-27 14:08:08.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/init/Kconfig 2004-07-27 13:58:19.000000000 +0200 @@ -294,6 +294,18 @@ If unsure, say N. +config GPIO + bool "GPIO pin support" + default y if ARM || PPC + default n + help + Enabling this option adds support for generic GPIO pins. Most + System-on-Chip processors have this kind of pins. + + FIXME: write more documentation. + + If unsure, say N. + endmenu # General setup diff -x .svn -urN linux-2.6.8-rc2/init/main.c linux-2.6.8-rc2-pnp1/init/main.c --- linux-2.6.8-rc2/init/main.c 2004-07-27 14:08:08.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/init/main.c 2004-07-27 13:58:19.000000000 +0200 @@ -447,6 +447,7 @@ * Interrupts are still disabled. Do necessary setups, then * enable them */ + lock_kernel(); page_address_init(); printk(linux_banner); diff -x .svn -urN linux-2.6.8-rc2/kernel/gpio.c linux-2.6.8-rc2-pnp1/kernel/gpio.c --- linux-2.6.8-rc2/kernel/gpio.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/kernel/gpio.c 2004-07-27 13:56:41.000000000 +0200 @@ -0,0 +1,374 @@ +/* + * linux/kernel/gpio.c + * + * (C) 2004 Robert Schwebel, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "gpio" + +static ssize_t gpio_show_level(struct class_device *dev, char *buf); +static ssize_t gpio_store_level(struct class_device *dev, const char *buf, size_t size); +static ssize_t gpio_show_policy(struct class_device *dev, char *buf); + +struct gpio_properties { + unsigned int pin_nr; + unsigned char policy; /* GPIO_xxx from above */ + char pin_level; /* -1=tristate, 0, 1 */ + char owner[20]; + struct gpio_device *gpio_dev; +}; + +struct gpio_device { + spinlock_t lock; /* protects the props field */ + struct gpio_properties props; + struct class_device class_dev; + struct list_head list; +}; +#define to_gpio_device(d) container_of(d, struct gpio_device, class_dev) + +static LIST_HEAD(gpio_list); +static rwlock_t gpio_list_lock = RW_LOCK_UNLOCKED; + +/* gpio_device is static, so we don't have to free it here */ +static void gpio_class_release(struct class_device *dev) +{ + return; +} + +static struct class gpio_class = { + .name = "gpio", + .release = gpio_class_release, +}; + + +/* + * Attribute: /sys/class/gpio/gpioX/level + */ +static struct class_device_attribute attr_gpio_level = { + .attr = { .name = "level", .mode = 0644, .owner = THIS_MODULE }, + .show = gpio_show_level, + .store = gpio_store_level, +}; + +static ssize_t gpio_show_level(struct class_device *dev, char *buf) +{ + struct gpio_device *gpio_dev = to_gpio_device(dev); + ssize_t ret_size = 0; + + if (gpio_dev->props.policy & GPIO_INPUT) + gpio_dev->props.pin_level = gpio_get_pin(gpio_dev->props.pin_nr); + + spin_lock(&gpio_dev->lock); + ret_size += sprintf(buf, "%i\n", gpio_dev->props.pin_level); + spin_unlock(&gpio_dev->lock); + + return ret_size; +} + +static ssize_t gpio_store_level(struct class_device *dev, const char *buf, size_t size) +{ + struct gpio_device *gpio_dev = to_gpio_device(dev); + long value; + + if (gpio_dev->props.policy & GPIO_INPUT) + return -EINVAL; + + value = simple_strtol(buf, NULL, 10); + if ((value != 0) && (value != 1)) + return -EINVAL; + gpio_dev->props.pin_level = value; + + /* set real hardware */ + switch (value) { + case 0: gpio_clear_pin(gpio_dev->props.pin_nr); + gpio_dir_output(gpio_dev->props.pin_nr); + break; + case 1: gpio_set_pin(gpio_dev->props.pin_nr); + gpio_dir_output(gpio_dev->props.pin_nr); + break; + default: break; + } + return size; +} + +/* + * Attribute: /sys/class/gpio/gpioX/policy + */ +static struct class_device_attribute attr_gpio_policy = { + .attr = { .name = "policy", .mode = 0444, .owner = THIS_MODULE }, + .show = gpio_show_policy, + .store = NULL, +}; + +static ssize_t gpio_show_policy(struct class_device *dev, char *buf) +{ + struct gpio_device *gpio_dev = to_gpio_device(dev); + ssize_t ret_size = 0; + + spin_lock(&gpio_dev->lock); + if (gpio_dev->props.policy & GPIO_USER) + ret_size += sprintf(buf,"userspace\n"); + if (gpio_dev->props.policy & GPIO_KERNEL) + ret_size += sprintf(buf,"kernel\n"); + spin_unlock(&gpio_dev->lock); + + return ret_size; +} + +static int gpio_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + char *p = page; + int size = 0; + struct gpio_device *gpio_dev; + struct list_head *lact, *ltmp; + + if (off != 0) + goto end; + + p += sprintf(p, "GPIO POLICY OWNER\n"); + list_for_each_safe(lact, ltmp, &gpio_list) { + gpio_dev = list_entry(lact, struct gpio_device, list); + p += sprintf(p, "%3i: ", gpio_dev->props.pin_nr); + if (gpio_dev->props.policy & GPIO_KERNEL) + p += sprintf(p, "kernel "); + if (gpio_dev->props.policy & GPIO_USER) + p += sprintf(p, "user space "); + p += sprintf(p, "%s\n", gpio_dev->props.owner); + } +end: + size = (p - page); + if (size <= off + count) + *eof = 1; + *start = page + off; + size -= off; + if (size > count) + size = count; + if (size < 0) + size = 0; + + return size; +} + +/** + * request_gpio - register a new object of gpio_device class. + * + * @pin_nr: GPIO pin which is registered + * @owner: name of the driver that owns this pin + * @policy: set policy for this pin, which is one of these: + * - GPIO_USER or GPIO_KERNEL + * - GPIO_INPUT or GPIO_OUTPUT + * For user space registered pins a sysfs entry is added. + * @init_level: initially configured pin level + */ +int request_gpio(unsigned int pin_nr, const char *owner, + unsigned char policy, unsigned char init_level) +{ + int rc; + struct gpio_device *gpio_dev; + struct list_head *lact, *ltmp; + + list_for_each_safe(lact, ltmp, &gpio_list) { + gpio_dev = list_entry(lact, struct gpio_device, list); + if (pin_nr == gpio_dev->props.pin_nr) { + printk(KERN_ERR "gpio pin %i is already used by %s\n", + pin_nr, gpio_dev->props.owner); + return -EBUSY; + } + } + + /* value checks - FIXME: is there a logical xor in C? */ + if ( ( (policy & GPIO_USER) && (policy & GPIO_KERNEL)) || + (!(policy & GPIO_USER) && !(policy & GPIO_KERNEL))) { + printk(KERN_ERR "%s: policy has to be one of GPIO_KERNEL, GPIO_USER\n", DRIVER_NAME); + return -EINVAL; + } + if ( ( (policy & GPIO_INPUT) && (policy & GPIO_OUTPUT)) || + (!(policy & GPIO_INPUT) && !(policy & GPIO_OUTPUT))) { + printk(KERN_ERR "%s: policy has to be one of GPIO_INPUT, GPIO_OUTPUT\n", DRIVER_NAME); + return -EINVAL; + } + + gpio_dev = kmalloc(sizeof(struct gpio_device), GFP_KERNEL); + + if (unlikely(!gpio_dev)) { + printk(KERN_ERR "%s: couldn't allocate memory\n", DRIVER_NAME); + return -ENOMEM; + } + + spin_lock_init(&gpio_dev->lock); + gpio_dev->props.pin_nr = pin_nr; + gpio_dev->props.policy = policy; + gpio_dev->props.pin_level = init_level; + gpio_dev->props.gpio_dev = gpio_dev; + strncpy(gpio_dev->props.owner, owner, 20); + + memset(&gpio_dev->class_dev, 0, sizeof(gpio_dev->class_dev)); + gpio_dev->class_dev.class = &gpio_class; + snprintf(gpio_dev->class_dev.class_id, BUS_ID_SIZE, "gpio%i", pin_nr); + + rc = class_device_register(&gpio_dev->class_dev); + if (unlikely(rc)) { + printk(KERN_ERR "%s: class registering failed\n", DRIVER_NAME); + kfree(gpio_dev); + return rc; + } + + INIT_LIST_HEAD(&gpio_dev->list); + + /* register the attributes */ + if (policy & GPIO_USER) + class_device_create_file(&gpio_dev->class_dev, &attr_gpio_level); + + class_device_create_file(&gpio_dev->class_dev, &attr_gpio_policy); + + /* set real hardware */ + if (policy & GPIO_OUTPUT) { + switch (init_level) { + case 0: gpio_clear_pin(pin_nr); break; + case 1: gpio_set_pin(pin_nr); break; + default: break; + } + gpio_dir_output(pin_nr); + } + + write_lock(&gpio_list_lock); + list_add_tail(&gpio_dev->list, &gpio_list); + write_unlock(&gpio_list_lock); + + printk(KERN_INFO "registered gpio%i\n", pin_nr); + + return 0; +} +EXPORT_SYMBOL(request_gpio); + +/** + * free_gpio - unregisters a object of gpio_properties class. + * + * @pin_nr: pin number to free. + * + * Unregisters a previously registered via request_gpio object. + */ +void free_gpio(unsigned int pin_nr) +{ + struct gpio_device *gpio_dev; + struct list_head *lact, *ltmp; + + list_for_each_safe(lact, ltmp, &gpio_list) { + gpio_dev = list_entry(lact, struct gpio_device, list); + if (pin_nr == gpio_dev->props.pin_nr) { + + printk(KERN_INFO "unregistering gpio pin %i\n", pin_nr); + + /* unregister attributes */ + if (gpio_dev->props.policy & GPIO_USER) + class_device_remove_file(&gpio_dev->class_dev, + &attr_gpio_level); + + class_device_remove_file(&gpio_dev->class_dev, &attr_gpio_level); + + class_device_unregister(&gpio_dev->class_dev); + write_lock(&gpio_list_lock); + list_del(&gpio_dev->list); + write_unlock(&gpio_list_lock); + kfree(gpio_dev); + return; + } + } +} +EXPORT_SYMBOL(free_gpio); + +void free_all_gpios(void) +{ + struct gpio_device *gpio_dev; + struct list_head *lact, *ltmp; + + list_for_each_safe(lact, ltmp, &gpio_list) { + gpio_dev = list_entry(lact, struct gpio_device, list); + + printk(KERN_INFO "unregistering gpio pin %i\n", gpio_dev->props.pin_nr); + + /* unregister attributes */ + if (gpio_dev->props.policy & GPIO_USER) + class_device_remove_file(&gpio_dev->class_dev, + &attr_gpio_level); + + class_device_remove_file(&gpio_dev->class_dev, &attr_gpio_level); + + class_device_unregister(&gpio_dev->class_dev); + write_lock(&gpio_list_lock); + list_del(&gpio_dev->list); + write_unlock(&gpio_list_lock); + kfree(gpio_dev); + return; + } +} +EXPORT_SYMBOL(free_all_gpios); + +static struct sysdev_class gpio_sysclass = { + set_kset_name("gpio"), +}; + +static struct sys_device gpio_sys_device = { + .id = 0, + .cls = &gpio_sysclass, +}; + +static int __init gpio_init(void) +{ + int ret; + + printk(KERN_INFO "Initialising gpio device class.\n"); + + class_register(&gpio_class); + + ret = sysdev_class_register(&gpio_sysclass); + if (ret) { + printk(KERN_ERR "%s: couldn't register sysdev class, exiting\n", DRIVER_NAME); + goto out_sysdev_class; + } + + ret = sysdev_register(&gpio_sys_device); + if (ret) { + printk(KERN_ERR "%s: couldn't register sysdev, exiting\n", DRIVER_NAME); + goto out_sysdev_register; + } + + if (!create_proc_read_entry ("gpio", 0, 0, gpio_read_proc, NULL)) { + printk(KERN_ERR "%s: couldn't register proc entry, exiting\n", DRIVER_NAME); + goto out_proc; + } + + return ret; + +out_proc: + sysdev_unregister(&gpio_sys_device); +out_sysdev_register: + sysdev_class_unregister(&gpio_sysclass); +out_sysdev_class: + class_unregister(&gpio_class); + return ret; +} + +__initcall(gpio_init); + +MODULE_AUTHOR("John Lenz, Robert Schwebel"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Generic GPIO Infrastructure"); + diff -x .svn -urN linux-2.6.8-rc2/kernel/Makefile linux-2.6.8-rc2-pnp1/kernel/Makefile --- linux-2.6.8-rc2/kernel/Makefile 2004-07-27 14:08:08.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/kernel/Makefile 2004-07-27 13:56:42.000000000 +0200 @@ -23,6 +23,7 @@ obj-$(CONFIG_STOP_MACHINE) += stop_machine.o obj-$(CONFIG_AUDIT) += audit.o obj-$(CONFIG_AUDITSYSCALL) += auditsc.o +obj-$(CONFIG_GPIO) += gpio.o ifneq ($(CONFIG_IA64),y) # According to Alan Modra , the -fno-omit-frame-pointer is diff -x .svn -urN linux-2.6.8-rc2/Makefile linux-2.6.8-rc2-pnp1/Makefile --- linux-2.6.8-rc2/Makefile 2004-07-27 14:08:03.000000000 +0200 +++ linux-2.6.8-rc2-pnp1/Makefile 2004-07-27 14:00:08.000000000 +0200 @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 8 -EXTRAVERSION =-rc2 +EXTRAVERSION =-rc2-ptxsvn NAME=Zonked Quokka # *DOCUMENTATION* @@ -182,8 +182,9 @@ # Default value for CROSS_COMPILE is not to prefix executables # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile -ARCH ?= $(SUBARCH) -CROSS_COMPILE ?= +# ARCH ?= $(SUBARCH) +ARCH ?= arm +CROSS_COMPILE ?= arm-softfloat-linux-gnu- # Architecture as present in compile.h UTS_MACHINE := $(ARCH) diff -x .svn -urN linux-2.6.8-rc2/README.PTX linux-2.6.8-rc2-pnp1/README.PTX --- linux-2.6.8-rc2/README.PTX 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.8-rc2-pnp1/README.PTX 2004-07-27 13:58:20.000000000 +0200 @@ -0,0 +1,11 @@ +README.PTX +---------- + +Apply these bkpxa patches: + +applied arm-fixes +applied arm-init-machine +applied pxa-serial +applied ipconfig + +Robert